Yahya M. Tousi

According to our database1, Yahya M. Tousi authored at least 13 papers between 2009 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
A mm-Wave Signal Generation and Background Phase Alignment Technique for Scalable Arrays.
IEEE J. Solid State Circuits, February, 2023

A Scalable Multi-Chip Self-Aligning Ka-Band Phased Array.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023

2021
Analysis of Stable Modes of a Scalable Coupled Oscillator Array.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

2018
Circuit and antenna-in-package innovations for scaled mmWave 5G phased array modules.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

2017
A 28-GHz 32-Element TRX Phased-Array IC With Concurrent Dual-Polarized Operation and Orthogonal Phase and Gain Control for 5G Communications.
IEEE J. Solid State Circuits, 2017

7.2 A 28GHz 32-element phased-array transceiver IC with concurrent dual polarized beams and 1.4 degree beam-steering resolution for 5G communication.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2015
A High-Power and Scalable 2-D Phased Array for Terahertz CMOS Integrated Systems.
IEEE J. Solid State Circuits, 2015

2014
14.6 A scalable THz 2D phased array with +17dBm of EIRP at 338GHz in 65nm bulk CMOS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2012
A Novel CMOS High-Power Terahertz VCO Based on Coupled Oscillators: Theory and Implementation.
IEEE J. Solid State Circuits, 2012

A 283-to-296GHz VCO with 0.76mW peak output power in 65nm CMOS.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2011
A Miniature 2 mW 4 bit 1.2 GS/s Delay-Line-Based ADC in 65 nm CMOS.
IEEE J. Solid State Circuits, 2011

2009
Delay-Line-Based Analog-to-Digital Converters.
IEEE Trans. Circuits Syst. II Express Briefs, 2009

A 1mW 4b 1GS/s delay-line based Analog-to-digital Converter.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009


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