Yahya Can Tugrul

Orcid: 0009-0002-9291-3626

According to our database1, Yahya Can Tugrul authored at least 20 papers between 2021 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

2021
2022
2023
2024
0
5
10
4
3
2
7
3
1

Legend:

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In proceedings 
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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Sectored DRAM: A Practical Energy-Efficient and High-Performance Fine-Grained DRAM Architecture.
ACM Trans. Archit. Code Optim., September, 2024

RowPress Vulnerability in Modern DRAM Chips.
IEEE Micro, 2024

Leveraging Adversarial Detection to Enable Scalable and Low Overhead RowHammer Mitigations.
CoRR, 2024

Ramulator 2.0: A Modern, Modular, and Extensible DRAM Simulator.
IEEE Comput. Archit. Lett., 2024

ABACuS: All-Bank Activation Counters for Scalable and Low Overhead RowHammer Mitigation.
Proceedings of the 33rd USENIX Security Symposium, 2024

BreakHammer: Enhancing RowHammer Mitigations by Carefully Throttling Suspect Threads.
Proceedings of the 57th IEEE/ACM International Symposium on Microarchitecture, 2024

Functionally-Complete Boolean Logic in Real DRAM Chips: Experimental Characterization and Analysis.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024

Spatial Variation-Aware Read Disturbance Defenses: Experimental Analysis of Real DRAM Chips and Implications on Future Solutions.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024

CoMeT: Count-Min-Sketch-based Row Tracking to Mitigate RowHammer at Low Cost.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024

Simultaneous Many-Row Activation in Off-the-Shelf DRAM Chips: Experimental Characterization and Analysis.
Proceedings of the 54th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2024

Read Disturbance in High Bandwidth Memory: A Detailed Experimental Study on HBM2 DRAM Chips.
Proceedings of the 54th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2024

2023
DRAM Bender: An Extensible and Versatile FPGA-Based Infrastructure to Easily Test State-of-the-Art DRAM Chips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023

PULSAR: Simultaneous Many-Row Activation for Reliable and High-Performance Computing in Off-the-Shelf DRAM Chips.
CoRR, 2023

Understanding Read Disturbance in High Bandwidth Memory: An Experimental Analysis of Real HBM2 DRAM Chips.
CoRR, 2023

RowPress: Amplifying Read Disturbance in Modern DRAM Chips.
Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023

DEV-PIM: Dynamic Execution Validation with Processing-in-Memory.
Proceedings of the IEEE European Test Symposium, 2023

An Experimental Analysis of RowHammer in HBM2 DRAM Chips.
Proceedings of the 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2023

2022
TuRaN: True Random Number Generation Using Supply Voltage Underscaling in SRAMs.
CoRR, 2022

Sectored DRAM: An Energy-Efficient High-Throughput and Practical Fine-Grained DRAM Architecture.
CoRR, 2022

2021
Uncovering In-DRAM RowHammer Protection Mechanisms: A New Methodology, Custom RowHammer Patterns, and Implications.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021


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