Ya Jun Yu
Orcid: 0000-0001-7374-3217
According to our database1,
Ya Jun Yu
authored at least 65 papers
between 2000 and 2020.
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Bibliography
2020
IEEE Access, 2020
2019
Proceedings of the IEEE International Conference on Engineering, Technology and Education, 2019
R-Peak Detection for ECG Signal Based on Local Maximums of Signal Magnitude and Correlation.
Proceedings of the 12th International Congress on Image and Signal Processing, 2019
2017
Lower Bound Analysis and Perturbation of Critical Path for Area-Time Efficient Multiple Constant Multiplications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
Investigation on power consumption of product accumulation block for multiplierless FIR filters.
Proceedings of the 22nd International Conference on Digital Signal Processing, 2017
2016
Analysis and Optimization of Product-Accumulation Section for Efficient Implementation of FIR Filters.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
Improved orthogonal frequency division multiplexing with generalised index modulation.
IET Commun., 2016
Greedy Algorithm for the Design of Linear-Phase FIR Filters with Sparse Coefficients.
Circuits Syst. Signal Process., 2016
Investigation on driver stress utilizing ECG signals with on-board navigation systems in use.
Proceedings of the 14th International Conference on Control, 2016
2015
IEEE Trans. Wirel. Commun., 2015
Two-Step Optimization Approach for the Design of Multiplierless Linear-Phase FIR Filters.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
New Approach to the Reduction of Sign-Extension Overhead for Efficient Implementation of Multiple Constant Multiplications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
Fine-Grained Critical Path Analysis and Optimization for Area-Time Efficient Realization of Multiple Constant Multiplications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the 2015 IEEE International Conference on Digital Signal Processing, 2015
2014
Bit-Level Multiplierless FIR Filter Optimization Incorporating Sparse Filter Technique.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
Improved Filter Bank Approach for the Design of Variable Bandedge and Fractional Delay Filters.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
A polynomial-time algorithm for the design of multiplierless linear-phase FIR filters with low hardware cost.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the IEEE Global Communications Conference, 2014
2013
Investigation on the Optimization Criteria for the Design of Variable Fractional Delay Filters.
IEEE Trans. Circuits Syst. II Express Briefs, 2013
Single-Stage and Cascade Design of High Order Multiplierless Linear Phase FIR Filters Using Genetic Algorithm.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
2012
Mixed-Radix Fast Filter Bank Approach for the Design of Variable Digital Filters With Simultaneously Tunable Bandedge and Fractional Delay.
IEEE Trans. Signal Process., 2012
Fixed-Point Analysis and Parameter Selections of MSR-CORDIC With Applications to FFT Designs.
IEEE Trans. Signal Process., 2012
Design of high order and wide coefficient wordlength multiplierless FIR filters with low hardware cost using genetic algorithm.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
2011
IEEE Trans. Circuits Syst. I Regul. Pap., 2011
Design of Linear Phase FIR Filters With High Probability of Achieving Minimum Number of Adders.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011
Implementation of Linear-Phase FIR Filters for a Rational Sampling-Rate Conversion Utilizing the Coefficient Symmetry.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011
Design of variable bandedge FIR filters with extremely large bandedge variation range.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Switching activity analysis and power estimation for multiple constant multiplier block of FIR filters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
2010
Implementation of Linear-Phase FIR Nearly Perfect Reconstruction Cosine-Modulated Filterbanks Utilizing the Coefficient Symmetry.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
Optimization of Linear Phase FIR Filters in Dynamically Expanding Subexpression Space.
Circuits Syst. Signal Process., 2010
Circuits Syst. Signal Process., 2010
Polynomial implementation structure for lagrange-type variable fractional delay filters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
2009
Low-Complexity Design of Variable Bandedge Linear Phase FIR Filters With Sharp Transition Band.
IEEE Trans. Signal Process., 2009
Design of Extrapolated Impulse Response FIR Filters With Residual Compensation in Subexpression Space.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
On the Complexity Reduction of Polyphase Linear Phase FIR Filters with Symmetric Coefficient Implementation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
2008
Subexpression encoded extrapolated impulse response FIR filter with perfect residual compensation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
2007
IEEE Trans. Signal Process., 2007
IEEE Trans. Signal Process., 2007
Design of Linear Phase FIR Filters in Subexpression Space Using Mixed Integer Linear Programming.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Roundoff Noise Analysis for FSK Signals in White Noise Represented as Signed Power-of-Two Numbers.
Proceedings of the 14th IEEE International Conference on Electronics, 2007
2006
An efficient implementation of linear-phase FIR filters for a rational sampling rate conversion.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
2005
Synthesis of very sharp Hilbert transformer using the frequency-response masking technique.
IEEE Trans. Signal Process., 2005
Optimum masking levels and coefficient sparseness for Hilbert transformers and half-band filters designed using the frequency-response masking technique.
IEEE Trans. Circuits Syst. I Regul. Pap., 2005
Extrapolated impulse response filter and its application in the synthesis of digital filters using the frequency-response masking technique.
Signal Process., 2005
Signed power-of-two allocation scheme for the design of lattice orthogonal filter banks.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
2004
Frequency-response-masking technique incorporating extrapolated impulse response band-edge shaping filter.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
An efficient algorithm for the optimization of FIR filters synthesized using the multistage frequency-response masking approach.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
2003
A width-recursive depth-first tree search approach for the design of discrete coefficient perfect reconstruction lattice filter bank.
IEEE Trans. Circuits Syst. II Express Briefs, 2003
An iterative method for optimizing FIR filters synthesized using the two-stage frequency-response masking technique.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
2002
IEEE Trans. Signal Process., 2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
Genetic algorithm approach for the optimization of multiplierless sub-filters generated by the frequency-response masking technique.
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002
2001
FPGA implementation of digital filters synthesized using the frequency-response masking technique.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
New natural selection process and chromosome encoding for the design of multiplierless lattice QMF using genetic algorithm.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001
2000
A successive reoptimization approach for the design of discrete coefficient perfect reconstruction lattice filter bank.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000