Ya-Cheng Lu

According to our database1, Ya-Cheng Lu authored at least 3 papers between 2002 and 2010.

Collaborative distances:
  • Dijkstra number2 of six.
  • Erdős number3 of four.

Timeline

Legend:

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2010
Concurrent Algorithm and Hardware Implementation for Low-Latency Turbo Decoder Using a Single MAP Decoder.
IEICE Trans. Commun., 2010

2005
Ringed bit-parallel systolic multipliers over a class of fields GF(2<sup><i>m</i></sup>).
Integr., 2005

2002
Low-complexity systolic multiplier over GF(2<sup>m</sup>) using weakly dual basis.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002


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