Y. Sudha Vani

According to our database, Y. Sudha Vani authored at least 2 papers in 2017.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2017

Low Write Energy STT-MRAM Cell Using 2T- Hybrid Tunnel FETs Exploiting the Steep Slope and Ambipolar Characteristics.

Y. Sudha Vani, N. Usha Rani, Ramesh Vaddi

Proceedings of the VLSI Design and Test - 21st International Symposium, 2017

A low voltage capacitor based current controlled sense amplifier for input offset compensation.

Y. Sudha Vani, N. Usha Rani, Ramesh Vaddi

Proceedings of the International SoC Design Conference, 2017