Y. N. Srikant

According to our database1, Y. N. Srikant authored at least 90 papers between 1982 and 2020.

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Bibliography

2020
IR2VEC: LLVM IR Based Scalable Program Embeddings.
ACM Trans. Archit. Code Optim., 2020

Distributed Graph Analytics.
Proceedings of the Distributed Computing and Internet Technology, 2020

Distributed Graph Analytics - Programming, Languages, and Their Compilation
Springer, ISBN: 978-3-030-41885-4, 2020

2019
IR2Vec: A Flow Analysis based Scalable Infrastructure for Program Encodings.
CoRR, 2019

2017
Refining Cache Behavior Prediction Using Cache Miss Paths.
ACM Trans. Embed. Comput. Syst., 2017

Presburger-Definable Parameterized Typestates.
CoRR, 2017

Beyond-Regular Typestate.
CoRR, 2017

Large Scale Graph Processing in a Distributed Environment.
Proceedings of the Euro-Par 2017: Parallel Processing Workshops, 2017

DH-Falcon: A Language for Large-Scale Graph Processing on Distributed Heterogeneous Systems.
Proceedings of the 2017 IEEE International Conference on Cluster Computing, 2017

2016
Fast and Precise Worst-Case Interference Placement for Shared Cache Analysis.
ACM Trans. Embed. Comput. Syst., 2016

Falcon: A Graph Manipulation Language for Heterogeneous Systems.
ACM Trans. Archit. Code Optim., 2016

Asynchrony-aware static analysis of Android applications.
Proceedings of the 2016 ACM/IEEE International Conference on Formal Methods and Models for System Design, 2016

2015
Path Sensitive Cache Analysis Using Cache Miss Paths.
Proceedings of the Verification, Model Checking, and Abstract Interpretation, 2015

Efficient Compilation of Stream Programs for Heterogeneous Architectures: A Model-Checking based approach.
Proceedings of the 18th International Workshop on Software and Compilers for Embedded Systems, 2015

2014
Toward a Scalable Working Set Size Estimation Method and Its Application for Chip Multiprocessors.
IEEE Trans. Computers, 2014

Exploiting critical data regions to reduce data cache energy consumption.
Proceedings of the 17th International Workshop on Software and Compilers for Embedded Systems, 2014

Precise shared cache analysis using optimal interference placement.
Proceedings of the 20th IEEE Real-Time and Embedded Technology and Applications Symposium, 2014

2012
Compiler-assisted energy optimization for clustered VLIW processors.
J. Parallel Distributed Comput., 2012

TCP: Thread Contention Predictor for Parallel Programs.
Proceedings of the 20th Euromicro International Conference on Parallel, 2012

Interdependent cache analyses for better precision and safety.
Proceedings of the Tenth ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2012

Efficient cache exploration method for a tiled chip multiprocessor.
Proceedings of the 19th International Conference on High Performance Computing, 2012

Estimation of probabilistic bounds on phase CPI and relevance in WCET analysis.
Proceedings of the 12th International Conference on Embedded Software, 2012

2011
Relative roles of instruction count and cycles per instruction in WCET estimation (abstracts only).
SIGMETRICS Perform. Evaluation Rev., 2011

Compiler-assisted power optimization for clustered VLIW architectures.
Parallel Comput., 2011

Relative roles of instruction count and cycles per instruction in WCET estimation.
Proceedings of the ICPE'11, 2011

Probabilistic dataflow analysis using path profiles on structure graphs.
Proceedings of the SIGSOFT/FSE'11 19th ACM SIGSOFT Symposium on the Foundations of Software Engineering (FSE-19) and ESEC'11: 13th European Software Engineering Conference (ESEC-13), 2011

Petri net based performance modeling for effective DVFS for multithreaded programs.
Proceedings of the 2011 ACM Symposium on Applied Computing (SAC), TaiChung, Taiwan, March 21, 2011

Applying genetic algorithms to optimize the power in tiled SNUCA chip multicore architectures.
Proceedings of the 2011 ACM Symposium on Applied Computing (SAC), TaiChung, Taiwan, March 21, 2011

Evaluation of dynamic voltage and frequency scaling for stream programs.
Proceedings of the 8th Conference on Computing Frontiers, 2011

Implications of Program Phase Behavior on Timing Analysis.
Proceedings of the 15th Workshop on Interaction between Compilers and Computer Architectures, 2011

2010
Accelerating multi-core simulators.
Proceedings of the 2010 ACM Symposium on Applied Computing (SAC), 2010

Integrated energy-aware cyclic and acyclic scheduling for clustered VLIW processors.
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

The Hot Path SSA Form: Extending the Static Single Assignment Form for Speculative Optimizations.
Proceedings of the Compiler Construction, 19th International Conference, 2010

2009
Probabilistic modeling of data cache behavior.
Proceedings of the 9th ACM & IEEE International conference on Embedded software, 2009

Profiling k-Iteration Paths: A Generalization of the Ball-Larus Profiling Algorithm.
Proceedings of the CGO 2009, 2009

2008
Pragmatic integrated scheduling for clustered VLIW architectures.
Softw. Pract. Exp., 2008

Improving flow-insensitive solutions for non-separable dataflow problems.
Proceedings of the 2008 ACM Symposium on Applied Computing (SAC), 2008

Analysis of application partitioning for massively multiplayer mobile gaming.
Proceedings of the 1st International Conference on MOBILe Wireless MiddleWARE, 2008

Test sequence computation for regression testing of reactive systems.
Proceedings of the Proceeding of the 1st Annual India Software Engineering Conference, 2008

Compiler-directed frequency and voltage scaling for a multiple clock domain microarchitecture.
Proceedings of the 5th Conference on Computing Frontiers, 2008

2007
Register File Energy Optimization for Snooping Based Clustered VLIW Architectures.
Proceedings of the 19th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2007), 2007

Executable Analysis using Abstract Interpretation with Circular Linear Progressions.
Proceedings of the 5th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2007), May 30, 2007

Partial Flow Sensitivity.
Proceedings of the High Performance Computing, 2007

Compiler-Assisted Instruction Decoder Energy Optimization for Clustered VLIW Architectures.
Proceedings of the High Performance Computing, 2007

WCET estimation for executables in the presence of data caches.
Proceedings of the 7th ACM & IEEE International conference on Embedded software, 2007

Microarchitecture Sensitive Empirical Models for Compiler Optimizations.
Proceedings of the Fifth International Symposium on Code Generation and Optimization (CGO 2007), 2007

INTACTE: an interconnect area, delay, and energy estimation tool for microarchitectural explorations.
Proceedings of the 2007 International Conference on Compilers, 2007

Energy-Aware Compiler Optimizations.
Proceedings of the Compiler Design Handbook: Optimizations and Machine Code Generation, 2007

The Static Single Assignment Form: Construction and Application to Program Optimization.
Proceedings of the Compiler Design Handbook: Optimizations and Machine Code Generation, 2007

2006
Middleware for efficient power management in mobile devices.
Proceedings of the 3rd international conference on Mobile technology, 2006

Specification Based Regression Testing Using Explicit State Space Enumeration.
Proceedings of the International Conference on Software Engineering Advances (ICSEA 2006), October 28, 2006

Exploring Energy-Performance Trade-Offs for Heterogeneous Interconnect Clustered VLIW Processors.
Proceedings of the High Performance Computing, 2006

Compiler-assisted leakage energy optimization for clustered VLIW architectures.
Proceedings of the 6th ACM & IEEE International conference on Embedded software, 2006

2005
Genetic algorithm based automatic data partitioning scheme for HPF.
Proceedings of the 14th IEEE International Symposium on High Performance Distributed Computing, 2005

A Programmable Hardware Path Profiler.
Proceedings of the 3nd IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2005), 2005

Transition aware scheduling: increasing continuous idle-periods in resource units.
Proceedings of the Second Conference on Computing Frontiers, 2005

2004
A Graph Matching Based Integrated Scheduling Framework for Clustered VLIW Processors.
Proceedings of the 33rd International Conference on Parallel Processing Workshops (ICPP 2004 Workshops), 2004

Integrated temporal and spatial scheduling for extended operand clustered VLIW processors.
Proceedings of the First Conference on Computing Frontiers, 2004

2003
Partial redundancy elimination: a simple, pragmatic, and provably correct algorithm.
Sci. Comput. Program., 2003

Dynamic recompilation and profile-guided optimisations for a .NET JIT compiler.
IEE Proc. Softw., 2003

A Simple and Fast Scheme for Code Compression for VLIW Processors.
Proceedings of the 2003 Data Compression Conference (DCC 2003), 2003

2002
On the use of connector libraries in distributed software architectures.
ACM SIGSOFT Softw. Eng. Notes, 2002

Scheduling expression trees for delayed-load architectures.
J. Syst. Archit., 2002

Improved Preprocessing Methods for Modulo Scheduling Algorithms.
Proceedings of the High Performance Computing, 2002

Scalar Compiler Optimizations on the Static Single Assignment Form and the Flow Graph.
Proceedings of the Compiler Design Handbook: Optimizations and Machine Code Generation, 2002

2000
A study of automatic migration of programs across the Java event models.
ACM SIGSOFT Softw. Eng. Notes, 2000

Effective Parameterization of Architectural Registers for Register Allocation Alogorithms.
ACM SIGPLAN Notices, 2000

1999
Automatic Data Partitioning by Hierarchical Genetic Search.
Parallel Algorithms Appl., 1999

The complexity of certain incremental code generation problems.
Int. J. Comput. Math., 1999

Hyperplane Partitioning: An Approach to Global Data Partitioning for Distributed Memory Machines.
Proceedings of the 13th International Parallel Processing Symposium / 10th Symposium on Parallel and Distributed Processing (IPPS / SPDP '99), 1999

1998
A Simple Algorithm for Partial Redundancy Elimination.
ACM SIGPLAN Notices, 1998

An incremental basic block instruction scheduler.
J. Syst. Archit., 1998

1997
Communication cost estimation and global data partitioning for distributed memory machines.
Proceedings of the Fourth International on High-Performance Computing, 1997

1995
Scheduling Expression Trees with Reusable Registers on Delayed-Load Architectures.
Comput. Lang., 1995

1994
Scheduliing expression trees with register variables on delayed-load architectures.
Microprocess. Microprogramming, 1994

Parallel Incremental LR Parsing.
Comput. Lang., 1994

An Automatic Parallelization Framework for Multicomputers.
Comput. Lang., 1994

1993
Heuristic Chaining in Directed Acyclic Graphs.
Comput. Lang., 1993

Linda Sub System on Transputers.
Comput. Lang., 1993

1991
Parallel Incremental LR Parsing.
Proceedings of the International Conference on Parallel Processing, 1991

1990
Parallel Parsing of Arithmetic Expressions.
IEEE Trans. Computers, 1990

Incremental Recursive Descent Parsing.
Comput. Lang., 1990

1989
A Class of Problems Efficiently Solvable on Mesh-Connected Computers Including Dynamic Expression Evaluation.
Inf. Process. Lett., 1989

Incremental Attribute Evaluation Through Recursive Procedures.
Comput. Lang., 1989

1988
A Compiler Writing System Based on Affix Grammars.
Comput. Lang., 1988

1987
A new parallel algorithm for parsing arithmetic infix expressions.
Parallel Comput., 1987

Parallel parsing of programming languages.
Inf. Sci., 1987

1986
An Interpreter for SLIPS - An Applicative Language Based on Lambda-Calculus.
Comput. Lang., 1986

Graphical simulation of Petri Nets.
Comput. Graph., 1986

1982
An interactive graphics system for 2-D drawing and design.
Comput. Graph., 1982


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