Y. Jaya Satyanarayana

Orcid: 0000-0002-9880-8985

Affiliations:

University of Pavia, Department of Electrical, Computer and Biomedical Engineering, Italy
National Institute of Technology Goa, Department of Electronics and Communication Engineering, Ponda, India

According to our database¹, Y. Jaya Satyanarayana authored at least 3 papers between 2020 and 2023.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of five.

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2023

A SAR-assisted Incremental $\Sigma\Delta$ ADC with Accumulation-based S/H Circuit for Shunt Current Measurements.

[BibT_eX]

[DOI]

Jaya Satyanarayana Yarragunta

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Thermal Noise Analysis of Accumulation-based S/H Circuit for Shunt Current Sensing.

[BibT_eX]

[DOI]

Jaya Satyanarayana Yarragunta

Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023

2020

A 1-V, 3-GHz Strong-Arm Latch Voltage Comparator for High Speed Applications.

[BibT_eX]

[DOI]

Siddharth R. K.

Y. Jaya Satyanarayana

Nithin Y. B. Kumar

M. H. Vasantha

Edoardo Bonizzoni

IEEE Trans. Circuits Syst., 2020

Y. Jaya Satyanarayana

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