Xunwei Wu

According to our database1, Xunwei Wu authored at least 21 papers between 1991 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Research on Indoor Mobile Robot Localization Method Based on Improved MCL.
Proceedings of the 8th International Conference on Robotics, Control and Automation, 2024

Fuzzy Adaptive Second Order Terminal Sliding Mode Trajectory Tracking Control for Robotic Manipulator.
Proceedings of the 8th International Conference on Robotics, Control and Automation, 2024

2003
Power Minimization of FPRM Functions Based on Polarity Conversion.
J. Comput. Sci. Technol., 2003

2002
Low power DCVSL circuits employing AC power supply.
Sci. China Ser. F Inf. Sci., 2002

Design of Ternary Schmitt Triggers Based on Its Sequential Characteristics.
Proceedings of the 32nd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2002), 2002

2000
Novel ?-Type Resistor Network in D/A Converter Based on Multiple-Valued Logic.
Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic, 2000

Propagation Algorithm of Behavior Probability in Power Estimation Based on Multiple-Valued Logic.
Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic, 2000

Low power sequential circuit design by using priority encoding and clock gating.
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000

Low-power design of sequential circuits using a quasi-synchronous derived clock.
Proceedings of ASP-DAC 2000, 2000

Analysis of power-clocked CMOS with application to the design of energy-recovery circuits.
Proceedings of ASP-DAC 2000, 2000

1999
Bounded algebra and current-mode digital circuits.
J. Comput. Sci. Technol., 1999

1998
A New Design for Double Edge Triggered Flip-flops.
Proceedings of the ASP-DAC '98, 1998

1997
Design of Ternary CCD Circuits Referencing to Current-Mode CMOS Circuits.
Proceedings of the 27th IEEE International Symposium on Multiple-Valued Logic, 1997

Comparison between nMos Pass Transistor logic style vs. CMOS Complementary Cells.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

A note on the relationship between signal probability and switching activity.
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

A new description of CMOS circuits at switch-level.
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

1996
Design technique of I<sup>2</sup>L circuits based on multi-valued logic.
J. Comput. Sci. Technol., 1996

1995
Race-Hazard and Skip-Hazard in Multivalued Combinational Circuits.
Proceedings of the 25th IEEE International Symposium on Multiple-Valued Logic, 1995

The High-Speed Ternary Logic Gates Based on the Multiple beta Transistors.
Proceedings of the 25th IEEE International Symposium on Multiple-Valued Logic, 1995

1992
The Theory of Clipping Voltage-Switches and Design of Quaternary nMOS Circuits.
Proceedings of the 22nd IEEE International Symposium on Multiple-Valued Logic, 1992

1991
Theory of Grounded Current Switches and Quatemary IIL Circuits.
Proceedings of the 21st International Symposium on Multiple-Valued Logic, 1991


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