Xuerong Jia

According to our database, Xuerong Jia authored at least 2 papers in 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of five.

2023

A Low-Cost Reduced-Latency DRAM Architecture With Dynamic Reconfiguration of Row Decoder.

Fujun Bai, Song Wang, Xuerong Jia, Yixin Guo, Bing Yu, Hang Wang, Cong Lai, Qiwei Ren, Hongbin Sun

IEEE Trans. Very Large Scale Integr. Syst., 2023

A 135 GBps/Gbit 0.66 pJ/bit Stacked Embedded DRAM with Multilayer Arrays by Fine Pitch Hybrid Bonding and Mini-TSV.

Song Wang, Bing Yu, Wenwu Xiao, Fujun Bai, Xiaodong Long, Liang Bai, Xuerong Jia, Fengguo Zuo, Jie Tan, Yixin Guo, Peng Sun, Jun Zhou, Qiong Zhan, Sheng Hu, Yu Zhou, Yi Kang, Qiwei Ren, Xiping Jiang

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023