Xueliang Wei

Orcid: 0000-0003-3571-1702

According to our database¹, Xueliang Wei authored at least 22 papers between 2009 and 2024.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of three.

Timeline

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On csauthors.net:

Bibliography

2024

Enabling Reliable Memory-Mapped I/O With Auto-Snapshot for Persistent Memory Systems.

[BibT_eX]

[DOI]

IEEE Trans. Computers, September, 2024

CMD: A Cache-assisted GPU Memory Deduplication Architecture.

[BibT_eX]

[DOI]

CoRR, 2024

A Read Latency Variation Aware Independent Read Scheme for QLC SSDs.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023

SplitZNS: Towards an Efficient LSM-Tree on Zoned Namespace SSDs.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., September, 2023

A Low-Latency and High-Endurance MLC STT-MRAM-Based Cache System.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023

Accelerating Persistent Hash Indexes via Reducing Negative Searches.

[BibT_eX]

[DOI]

Proceedings of the 41st IEEE International Conference on Computer Design, 2023

LifetimeKV: Narrowing the Lifetime Gap of SSTs in LSMT-based KV Stores for ZNS SSDs.

[BibT_eX]

[DOI]

Proceedings of the 41st IEEE International Conference on Computer Design, 2023

ODLPIM: A Write-Optimized and Long-Lifetime ReRAM-Based Accelerator for Online Deep Learning.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022

RMMIO: Enabling Reliable Memory-Mapped I/O for Persistent Memory Systems.

[BibT_eX]

[DOI]

Proceedings of the IEEE 40th International Conference on Computer Design, 2022

2021

Improving Multilevel Writes on Vertical 3-D Cross-Point Resistive Memory.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Multi-task prediction model based on ConvLSTM and encoder-decoder.

[BibT_eX]

[DOI]

Intell. Data Anal., 2021

Write-Optimized and Consistent Skiplists for Non-Volatile Memory.

[BibT_eX]

[DOI]

IEEE Access, 2021

Crash-Consistency-Aware Encryption for Non-Volatile Memories.

[BibT_eX]

[DOI]

Proceedings of the ICPP 2021: 50th International Conference on Parallel Processing, Lemont, IL, USA, August 9, 2021

2020

Hybrid Codes: Flexible Erasure Codes with Optimized Recovery Performance.

[BibT_eX]

[DOI]

ACM Trans. Storage, 2020

STC: Sub-packetization tunable codes for fast recovery.

[BibT_eX]

[DOI]

J. Syst. Archit., 2020

MorLog: Morphable Hardware Logging for Atomic Persistence in Non-Volatile Main Memory.

[BibT_eX]

[DOI]

Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

CCHL: Compression-Consolidation Hardware Logging for Efficient Failure-Atomic Persistent Memory Updates.

[BibT_eX]

[DOI]

Proceedings of the ICPP 2020: 49th International Conference on Parallel Processing, 2020

2019

NICO: Reducing Software-Transparent Crash Consistency Cost for Persistent Memory.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2019

A Generic Construction for All Parameters in Minimum Storage Regenerating Codes.

[BibT_eX]

[DOI]

Proceedings of the 38th Symposium on Reliable Distributed Systems, 2019

2010

Shunt APF Based on Current Loop Repetitive Control.

[BibT_eX]

[DOI]

Xueliang Wei

J. Convergence Inf. Technol., 2010

A signal-noise model for significance analysis of ChIP-seq with negative control.

[BibT_eX]

[DOI]

Bioinform., 2010

2009

Computer Control Design of Active Power Filter Based on the Energy Shaping Control Principle.

[BibT_eX]

[DOI]

Proceedings of the CSIE 2009, 2009 WRI World Congress on Computer Science and Information Engineering, March 31, 2009

Xueliang Wei

Timeline

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