Xuejue Huang
According to our database1,
Xuejue Huang
authored at least 9 papers
between 2000 and 2005.
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Bibliography
2005
IEEE Trans. Very Large Scale Integr. Syst., 2005
Impact of on-chip interconnect frequency-dependent R(f)L(f) on digital and RF design.
IEEE Trans. Very Large Scale Integr. Syst., 2005
2003
Improved a priori interconnect predictions and technology extrapolation in the GTX system.
IEEE Trans. Very Large Scale Integr. Syst., 2003
Loop-based interconnect modeling and optimization approach for multigigahertz clock network design.
IEEE J. Solid State Circuits, 2003
IEEE J. Solid State Circuits, 2003
2002
Effective on-chip inductance modeling for multiple signal lines and application to repeater insertion.
IEEE Trans. Very Large Scale Integr. Syst., 2002
Loop-based interconnect modeling and optimization approach for multi-GHz clock network design.
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002
2001
Effective On-chip Inductance Modeling for Multiple Signal Lines and Application on Repeater Insertion.
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001
2000
Effects of Global Interconnect Optimizations on Performance Estimation of Deep Submicron Design.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000