Xuegong Zhou

Orcid: 0000-0003-4178-4094

According to our database¹, Xuegong Zhou authored at least 40 papers between 2004 and 2024.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

Legend:

Book

In proceedings

Article

PhD thesis

Dataset

Other

Links

On csauthors.net:

Bibliography

2024

An Efficient Reinforcement Learning Based Framework for Exploring Logic Synthesis.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., March, 2024

An Open-source End-to-End Logic Optimization Framework for Large-scale Boolean Network with Reinforcement Learning.

[BibT_eX]

[DOI]

CoRR, 2024

2023

An Optimized GIB Routing Architecture with Bent Wires for FPGA.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., March, 2023

DSLUT: An Asymmetric LUT and its Automatic Design Flow Based on Practical Functions.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field Programmable Technology, 2023

AMG: Automated Efficient Approximate Multiplier Generator for FPGAs via Bayesian Optimization.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field Programmable Technology, 2023

2022

Efficient Reinforcement Learning Framework for Automated Logic Synthesis Exploration.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field-Programmable Technology, 2022

2021

MRI-based brain tumor segmentation using FPGA-accelerated neural network.

[BibT_eX]

[DOI]

BMC Bioinform., 2021

FastCGRA: A Modeling, Evaluation, and Exploration Platform for Large-Scale Coarse-Grained Reconfigurable Arrays.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field-Programmable Technology, 2021

2020

Fast Exact NPN Classification by Co-Designing Canonical Form and Its Computation Algorithm.

[BibT_eX]

[DOI]

Xuegong Zhou

Lingli Wang

Alan Mishchenko

IEEE Trans. Computers, 2020

GIB: A Novel Unidirectional Interconnection Architecture for FPGA.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field-Programmable Technology, 2020

A Low-Cost Reconfigurable Nonlinear Core for Embedded DNN Applications.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field-Programmable Technology, 2020

2019

Fast Adjustable NPN Classification Using Generalized Symmetries.

[BibT_eX]

[DOI]

Xuegong Zhou

Lingli Wang

Alan Mishchenko

ACM Trans. Reconfigurable Technol. Syst., 2019

ARBSA: Adaptive Range-Based Simulated Annealing for FPGA Placement.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

A Complete CPU-FPGA Architecture for Protein Identification with Tandem Mass Spectrometry.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field-Programmable Technology, 2019

2018

Fast Adjustable NPN Classification using Generalized Symmetries.

[BibT_eX]

[DOI]

Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

2017

RBSA: Range-based simulated annealing for FPGA placement.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field Programmable Technology, 2017

A scalable hybrid architecture for high performance data-parallel applications.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field Programmable Technology, 2017

Accelerating low bit-width convolutional neural networks with embedded FPGA.

[BibT_eX]

[DOI]

Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

An on-line debug method for FPGAs.

[BibT_eX]

[DOI]

Yipeng Yuan

Zhihua Feng

Xuegong Zhou

Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016

High performance Deformable Part Model accelerator based on FPGA.

[BibT_eX]

[DOI]

Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

A high performance FPGA-based accelerator for large-scale convolutional neural networks.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

2015

An adaptive cross-layer fault recovery solution for reconfigurable SoCs.

[BibT_eX]

[DOI]

Proceedings of the 2015 International Conference on Field Programmable Technology, 2015

UniStream: A unified stream architecture combining configuration and data processing.

[BibT_eX]

[DOI]

Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

An automated test framework for SRAM-based FPGA.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2013

SPREAD: A Streaming-Based Partially Reconfigurable Architecture and Programming Model.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

A hardware implementation of Bag of Words and Simhash for image recognition.

[BibT_eX]

[DOI]

Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

An FPGA-cluster-accelerated match engine for content-based image retrieval.

[BibT_eX]

[DOI]

Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

Implementation of high performance hardware architecture of OpenSURF algorithm on FPGA.

[BibT_eX]

[DOI]

Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

A reconfigurable floating-point FFT architecture.

[BibT_eX]

[DOI]

Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012

A partially reconfigurable architecture supporting hardware threads.

[BibT_eX]

[DOI]

Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

2011

Automatic layout generator for embedded FPGA cores.

[BibT_eX]

[DOI]

Chaofan Yu

Lingli Wang

Xuegong Zhou

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2010

General switch box modeling and optimization for FPGA routing architectures.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field-Programmable Technology, 2010

2007

Fast On-line Task Placement and Scheduling on Reconfigurable Devices.

[BibT_eX]

[DOI]

Proceedings of the FPL 2007, 2007

Online Task Scheduling for Heterogeneous Reconfigurable Systems.

[BibT_eX]

[DOI]

Proceedings of the Computer Supported Cooperative Work in Design IV, 2007

Online Hybrid Task Scheduling in Reconfigurable Systems.

[BibT_eX]

[DOI]

Proceedings of the 11th International Conference on Computer Supported Cooperative Work in Design, 2007

2006

System Prototyping Based on SystemC Transaction-Level Modeling.

[BibT_eX]

[DOI]

Proceedings of the Interdisciplinary and Multidisciplinary Research in Computer Science, 2006

On-line scheduling of real-time tasks for reconfigurable computing system.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

A MDA based SoC Modeling Approach using UML and SystemC.

[BibT_eX]

[DOI]

Proceedings of the Sixth International Conference on Computer and Information Technology (CIT 2006), 2006

2005

ESIDE - embedded system integrated design environment based on Eclipse platform.

[BibT_eX]

[DOI]

Proceedings of the Ninth International Conference on Computer Supported Cooperative Work in Design, 2005

2004

An Automatic Coverage Analysis for SystemC Using UML and Aspect-Oriented Technology.

[BibT_eX]

[DOI]

Proceedings of the Computer Supported Cooperative Work in Design I, 2004

Xuegong Zhou

Timeline

Legend:

Links

On csauthors.net:

Bibliography

Loading...