Xue Liu

Orcid: 0000-0003-4178-8749

Affiliations:
  • Northeastern University, School of Computer Science and Engineering, Shenyang, China


According to our database1, Xue Liu authored at least 10 papers between 2011 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2021
Understanding and Optimizing Conjunctive Predicates Under Memory-Efficient Storage Layouts.
IEEE Trans. Knowl. Data Eng., 2021

2020
Boyi: A Systematic Framework for Automatically Deciding the Right Execution Model of OpenCL Applications on FPGAs.
Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

2018
Hebe: An Order-Oblivious and High-Performance Execution Scheme for Conjunctive Predicates.
Proceedings of the 34th IEEE International Conference on Data Engineering, 2018

2017
Design and FPGA Implementation of a Reconfigurable Digital Down Converter for Wideband Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2017

FPGA implementation of a reconfigurable channelization for simultaneous multichannel DRM30/FM receiver.
IEEE Trans. Consumer Electron., 2017

2016
Design and FPGA Implementation of a Reconfigurable 1024-Channel Channelization Architecture for SDR Application.
IEEE Trans. Very Large Scale Integr. Syst., 2016

2015
A Combined SDC-SDF Architecture for Normal I/O Pipelined Radix-2 FFT.
IEEE Trans. Very Large Scale Integr. Syst., 2015

2014
High-speed, fixed-latency serial links with Xilinx FPGAs.
J. Zhejiang Univ. Sci. C, 2014

2013
Block Processor: A resource-distributed architecture.
Proceedings of the IEEE High Performance Extreme Computing Conference, 2013

2011
A pipelined architecture for normal I/O order FFT.
J. Zhejiang Univ. Sci. C, 2011


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