Xuansheng Ji

According to our database1, Xuansheng Ji authored at least 3 papers between 2022 and 2025.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

2022
2023
2024
2025
0
1
2
1
1
1

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2025
An Ultra-Low-Voltage Bias-Current-Free Fractional-N Hybrid PLL With Voltage-Mode Phase Detection and Interpolation.
IEEE J. Solid State Circuits, January, 2025

2024
14.7 A 0.45V 0.72mW 2.4GHz Bias-Current-Free Fractional-N Hybrid PLL Using a Voltage-Mode Phase Interpolator in 28nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2022
A 0.7-2.5GHz NB-loT/GNSS/BLE Hybrid PLL with PA Pulling Mitigation and Out-of-Band Phase Noise Reduction.
Proceedings of the 2022 IEEE International Conference on Integrated Circuits, 2022


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