Xuansheng Ji

According to our database, Xuansheng Ji authored at least 2 papers between 2022 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2024

14.7 A 0.45V 0.72mW 2.4GHz Bias-Current-Free Fractional-N Hybrid PLL Using a Voltage-Mode Phase Interpolator in 28nm CMOS.

Liqun Feng, Xuansheng Ji, Longhao Kuang, Qianxian Liao, Su Han, Jiahao Zhao, Woogeun Rhee, Zhihua Wang

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2022

A 0.7-2.5GHz NB-loT/GNSS/BLE Hybrid PLL with PA Pulling Mitigation and Out-of-Band Phase Noise Reduction.

Jiahao Zhao, Xuansheng Ji, Su Han, Ziwei Wang, Woogeun Rhee, Zhihua Wang

Proceedings of the 2022 IEEE International Conference on Integrated Circuits, 2022