Xuan-Yu Lin

According to our database, Xuan-Yu Lin authored at least 2 papers between 2015 and 2017.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2017

ULV-Turbo Cache for an Instantaneous Performance Boost on Asymmetric Architectures.

Po-Hao Wang, Yung-Chen Chien, Shang-Jen Tsai, Xuan-Yu Lin, Rizal Tanjung, Yi-Sian Lin, Shu-Wei Syu, Tay-Jyi Lin, Jinn-Shyan Wang, Tien-Fu Chen

IEEE Trans. Very Large Scale Integr. Syst., 2017

2015

Low-cost low-power droop-voltage-aware delay-fault-prevention designs for DVS caches.

Pei-Yuan Chou, I-Chen Wu, Jai-Wei Lin, Xuan-Yu Lin, Tien-Fu Chen, Tay-Jyi Lin, Jinn-Shyan Wang

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015