Xuan Wang

Affiliations:

Hong Kong University of Science and Technology, Department of Electronic and Computer Engineering, Hong Kong
Princeton University, NJ, USA (PhD 2007)
Sandbridge Technologies, White Plains, NY, USA (2005 - 2007)
NEC Laboratories America, Princeton, NJ, USA (2003 - 2005)
Bell Laboratories, NJ, USA (2001 - 2002)

According to our database¹, Xuan Wang authored at least 33 papers between 2010 and 2017.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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In proceedings

Article

PhD thesis

Dataset

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Links

On csauthors.net:

Bibliography

2017

Energy-Efficient Power Delivery System Paradigms for Many-Core Processors.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

2016

Improve Chip Pin Performance Using Optical Interconnects.

[BibT_eX]

[DOI]

Rafael Kioji Vivas Maeda

Haoran Li

IEEE Trans. Very Large Scale Integr. Syst., 2016

A Holistic Modeling and Analysis of Optical-Electrical Interfaces for Inter/Intra-chip Interconnects.

[BibT_eX]

[DOI]

Rafael Kioji Vivas Maeda

IEEE Trans. Very Large Scale Integr. Syst., 2016

An Adaptive Process-Variation-Aware Technique for Power-Gating-Induced Power/Ground Noise Mitigation in MPSoC.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

Distributed Sensor Network-on-Chip for Performance Optimization of Soft-Error-Tolerant Multiprocessor System-on-Chip.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

Coherent and Incoherent Crosstalk Noise Analyses in Interchip/Intrachip Optical Interconnection Networks.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

Alleviate Chip Pin Constraint for Multicore Processor by On/Off-Chip Power Delivery System Codesign.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2016

2015

An Inter/Intra-Chip Optical Network for Manycore Processors.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

Actively Alleviate Power Gating-Induced Power/Ground Noise Using Parasitic Capacitance of On-Chip Memories in MPSoC.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

Crosstalk Noise in WDM-Based Optical Networks-on-Chip: A Formal Study and Comparison.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

Fat-Tree-Based Optical Interconnection Networks Under Crosstalk Noise Constraint.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

An Analytical Study of Power Delivery Systems for Many-Core Processors Using On-Chip and Off-Chip Voltage Regulators.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Adaptively tolerate power-gating-induced power/ground noise under process variations.

[BibT_eX]

[DOI]

Rafael Kioji Vivas Maeda

Zhifei Wang

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Alleviate chip I/O pin constraints for multicore processors through optical interconnects.

[BibT_eX]

[DOI]

Rafael Kioji Vivas Maeda

Xiaowen Wu

Yaoyao Ye

Qinfen Hao

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014

UNION: A Unified Inter/Intrachip Optical Network for Chip Multiprocessors.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

System-Level Modeling and Analysis of Thermal Effects in WDM-Based Optical Networks-on-Chip.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Systematic Analysis of Crosstalk Noise in Folded-Torus-Based Optical Networks-on-Chip.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Floorplan Optimization of Fat-Tree-Based Networks-on-Chip for Chip Multiprocessors.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2014

SUOR: Sectioned Undirectional Optical Ring for Chip Multiprocessor.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2014

On-chip sensor networks for soft-error tolerant real-time multiprocessor systems-on-chip.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2014

Characterizing power delivery systems with on/off-chip voltage regulators for many-core processors.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013

System-Level Modeling and Analysis of Thermal Effects in Optical Networks-on-Chip.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

Formal Worst-Case Analysis of Crosstalk Noise in Mesh-Based Optical Networks-on-Chip.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

On-Chip Sensor Network for Efficient Management of Power Gating-Induced Power/Ground Noise in Multiprocessor System on Chip.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2013

3-D Mesh-Based Optical Network-on-Chip for Multiprocessor System-on-Chip.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

On-line fast palmprint identification based on adaptive lifting wavelet scheme.

[BibT_eX]

[DOI]

Xuan Wang

Junhua Liang

Mingzhe Wang

Knowl. Based Syst., 2013

System-level analysis of mesh-based hybrid optical-electronic network-on-chip.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Active power-gating-induced power/ground noise alleviation using parasitic capacitance of on-chip memories.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

2011

Modeling and Analysis of Thermal Effects in Optical Networks-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

A NoC Traffic Suite Based on Real Applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

A Hardware-Software Collaborated Method for Soft-Error Tolerant MPSoC.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

2010

UNION: A unified inter/intra-chip optical network for chip multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, 2010

Crosstalk noise and bit error rate analysis for optical network-on-chip.

[BibT_eX]

[DOI]

Proceedings of the 47th Design Automation Conference, 2010

Xuan Wang

Timeline

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