Xuan-Tu Tran
Orcid: 0000-0003-4259-9579
According to our database1,
Xuan-Tu Tran
authored at least 55 papers
between 2006 and 2024.
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Online presence:
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Bibliography
2024
A light-weight neuromorphic controlling clock gating based multi-core cryptography platform.
Microprocess. Microsystems, 2024
2023
An In-Situ Dynamic Quantization With 3D Stacking Synaptic Memory for Power-Aware Neuromorphic Architecture.
IEEE Access, 2023
Low-cost Low-Power Implementation of Binary Edwards Curve for Secure Passive RFID Tags.
Proceedings of the 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2023
2022
A low-power, high-accuracy with fully on-chip ternary weight hardware architecture for Deep Spiking Neural Networks.
Microprocess. Microsystems, April, 2022
Design and Implementation of a Coarse-grained Dynamically Reconfigurable Multimedia Accelerator.
ACM Trans. Parallel Comput., 2022
HotCluster: A Thermal-Aware Defect Recovery Method for Through-Silicon-Vias Toward Reliable 3-D ICs Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Composite Lightweight Authenticated Encryption Based on LED Block Cipher and PHOTON Hash Function for IoT Devices.
Proceedings of the 15th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2022
GAQ-SNN: A Genetic Algorithm based Quantization Framework for Deep Spiking Neural Networks.
Proceedings of the International Conference on IC Design and Technology, 2022
Proceedings of the International Conference on IC Design and Technology, 2022
2021
A Sub-μ W Reversed-Body-Bias 8-bit Processor on 65-nm Silicon-on-Thin-Box (SOTB) for IoT Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
A trigonometric hardware acceleration in 32-bit RISC-V microcontroller with custom instruction.
IEICE Electron. Express, 2021
A proposal for enhancing training speed in deep learning models based on memory activity survey.
IEICE Electron. Express, 2021
2020
TSV-OCT: A Scalable Online Multiple-TSV Defects Localization for Real-Time 3-D-IC Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2020
Reducing Bitrate and Increasing the Quality of Inter Frame by Avoiding Quantization Errors in Stationary Blocks.
EAI Endorsed Trans. Ind. Networks Intell. Syst., 2020
Low-power high-performance 32-bit RISC-V microcontroller on 65-nm silicon-on-thin-BOX (SOTB).
IEICE Electron. Express, 2020
CoRR, 2020
A Non-Blocking Non-Degrading Multiple Defects Link Testing Method for 3D-Networks-on-Chip.
IEEE Access, 2020
A Thermal-Aware On-Line Fault Tolerance Method for TSV Lifetime Reliability in 3D-NoC Systems.
IEEE Access, 2020
FPGA-Based Lightweight Hardware Architecture of the PHOTON Hash Function for IoT Edge Devices.
IEEE Access, 2020
A lightweight Max-Pooling method and architecture for Deep Spiking Convolutional Neural Networks.
Proceedings of the 2020 IEEE Asia Pacific Conference on Circuits and Systems, 2020
Proceedings of the 2020 IEEE Asia Pacific Conference on Circuits and Systems, 2020
Low-Power Implementation of a High-Throughput Multi-core AES Encryption Architecture.
Proceedings of the 2020 IEEE Asia Pacific Conference on Circuits and Systems, 2020
2019
J. Syst. Archit., 2019
An Efficient Event-driven Neuromorphic Architecture for Deep Spiking Neural Networks.
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019
An on-Communication Multiple-TSV Defects Detection and Localization for Real-Time 3D-ICs.
Proceedings of the 13th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2019
TSV-IaS: Analytic Analysis and Low-Cost Non-Preemptive on-Line Detection and Correction Method for TSV Defects.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019
Proceedings of the 19th International Symposium on Communications and Information Technologies, 2019
A Wideband High Efficiency Ka-Band MMIC Power Amplifier for 5G Wireless Communications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Proceedings of the 2019 IEEE Asia Pacific Conference on Circuits and Systems, 2019
2D-PPC: A single-correction multiple-detection method for Through-Silicon-Via Faults.
Proceedings of the 2019 IEEE Asia Pacific Conference on Circuits and Systems, 2019
2018
Parity-Based ECC and Mechanism for Detecting and Correcting Soft Errors in On-Chip Communication.
Proceedings of the 12th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2018
Proceedings of the 2018 International Conference on IC Design & Technology, 2018
2017
A Comprehensive Reliability Assessment of Fault-Resilient Network-on-Chip Using Analytical Model.
IEEE Trans. Very Large Scale Integr. Syst., 2017
AES Datapath Optimization Strategies for Low-Power Low-Energy Multisecurity-Level Internet-of-Things Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2017
AXI-NoC: High-Performance Adaptation Unit for ARM Processors in Network-on-Chip Architectures.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017
Power consumption estimation using VNOC2.0 simulator for a fuzzy-logic based low power Network-on-Chip.
Proceedings of the 2017 IEEE International Conference on IC Design and Technology, 2017
2016
Ultra low-power and low-energy 32-bit datapath AES architecture for IoT applications.
Proceedings of the International Conference on IC Design and Technology, 2016
2015
Proceedings of the IEEE 7th International Conference on Awareness Science and Technology, 2015
2014
Proceedings of the IECON 2014 - 40th Annual Conference of the IEEE Industrial Electronics Society, Dallas, TX, USA, October 29, 2014
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014
2013
Simul. Model. Pract. Theory, 2013
Proceedings of the 2013 IEEE International SOC Conference, Erlangen, Germany, 2013
Proceedings of the Multimedia and Ubiquitous Engineering, 2013
2012
Proceedings of the 26th Pacific Asia Conference on Language, Information and Computation, 2012
2011
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011
2010
Proceedings of the International Conference on Asian Language Processing, 2010
2009
IEEE J. Solid State Circuits, 2009
Design-for-test approach of an asynchronous network-on-chip architecture and its associated test pattern generation and application.
IET Comput. Digit. Tech., 2009
2008
A Design-for-Test Implementation of an Asynchronous Network-on-Chip Architecture and its Associated Test Pattern Generation and Application.
Proceedings of the Second International Symposium on Networks-on-Chips, 2008
2007
Proceedings of the First International Symposium on Networks-on-Chips, 2007
2006
Proceedings of the 11th European Test Symposium, 2006
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006