Xuan-Thuan Nguyen

Orcid: 0000-0002-3963-8728

According to our database1, Xuan-Thuan Nguyen authored at least 36 papers between 2012 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

2012
2014
2016
2018
2020
2022
2024
0
1
2
3
4
5
6
7
8
3
1
1
1
3
4
3
2
1
1
2
3
3
3
4
1

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
Application of hedge algebras algorithm for mobile robot controller via hand gestures and wireless protocol.
J. Intell. Fuzzy Syst., January, 2024

Design and Implementation of Hedge Algebra Controller using Recursive Semantic Values for Cart-pole System.
CoRR, 2024

Hybrid Gripper with Passive Pneumatic Soft Joints for Grasping Deformable Thin Objects.
CoRR, 2024

2023
A Controller for Delta Parallel Robot Based on Hedge Algebras Method.
J. Robotics, 2023

2022
Mobile Robot Motion Control Using a Combination of Fuzzy Logic Method and Kinematic Model.
CoRR, 2022

2020
A 0.9-V 50-MHz 256-bit 1D-to-2D-based single/multi-match priority encoder with 0.67-nW standby power on 65-nm SOTB CMOS.
Microprocess. Microsystems, 2020

Nonlinearities Output-Feedback Adaptive Nonsingular Fast Terminal Sliding Mode Control for Redundant Parallel Manipulators.
Proceedings of the International Conference on System Science and Engineering, 2020

2019
An Efficient I/O Architecture for RAM-Based Content-Addressable Memory on FPGA.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

Low-Power Floating-Point Adaptive-CORDIC-Based FFT Twiddle Factor on 65-nm Silicon-on-Thin-BOX (SOTB) With Back-Gate Bias.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

A 1.2-V 162.9 pJ/cycle bitmap index creation core with 0.31-pW/bit standby power on 65-nm SOTB.
Microprocess. Microsystems, 2019

Adaptively Clock-Boosted Auto-Ranging Responsive Neurostimulator for Emerging Neuromodulation Applications.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

A 1.2-V 90-MHz Bitmap Index Creation Accelerator with 0.27-nW Standby Power on 65-nm Silicon-On-Thin-Box (SOTB) CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018
A Low-Power Hybrid Adaptive CORDIC.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

A High-Throughput Low-Energy Arithmetic Processor.
IEICE Trans. Electron., 2018

A CORDIC-based QR decomposition for MIMO signal detector.
IEICE Electron. Express, 2018

An FPGA-Based Hardware Accelerator for Energy-Efficient Bitmap Index Creation.
IEEE Access, 2018

VLSI Design of Frequent Items Counting Using Binary Decoders Applied to 8-bit per Item Case-study.
Proceedings of the 14th Conference on Ph.D. Research in Microelectronics and Electronics, 2018

A 219-μW 1D-to-2D-Based Priority Encoder on 65-nm SOTB CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

An efficient fixed-point arithmetic processor using a hybrid CORDIC algorithm.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
A Scalable High-Performance Priority Encoder Using 1D-Array to 2D-Array Conversion.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

A Low-Latency Parallel Pipeline CORDIC.
IEICE Trans. Electron., 2017

A Flexible High-Bandwidth Low-Latency Multi-Port Memory Controller.
CoRR, 2017

FPGA-based frequent items counting using matrix of equality comparators.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Reliable and energy-efficient transmission on the Internet-of-Video-Things.
Proceedings of the 17th International Symposium on Communications and Information Technologies, 2017

Highly parallel bitmap-based regular expression matching for text analytics.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016
An FPGA approach for high-performance multi-match priority encoder.
IEICE Electron. Express, 2016

An FPGA approach for fast bitmap indexing.
IEICE Electron. Express, 2016

An efficient FPGA-based database processor for fast database analytics.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A hybrid adaptive CORDIC in 65nm SOTB CMOS process.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A high-throughput and low-power design for bitmap indexing on 65-nm SOTB CMOS process.
Proceedings of the International Conference on IC Design and Technology, 2016

2015
Low-resource low-latency hybrid adaptive CORDIC with floating-point precision.
IEICE Electron. Express, 2015

Parallel pipelining configurable multi-port memory controller for multimedia applications.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

SAR: A Self-Adaptive and Reliable protocol for wireless multimedia sensor networks.
Proceedings of the Seventh International Conference on Ubiquitous and Future Networks, 2015

Design of a low-power fixed-point 16-bit digital signal processor using 65nm SOTB process.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015

An efficient multi-port memory controller for multimedia applications.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2012
A real-time DSP-based hand gesture recognition system.
Proceedings of the IEEE International Symposium on Signal Processing and Information Technology, 2012


  Loading...