Xuan-Lun Huang

According to our database, Xuan-Lun Huang authored at least 17 papers between 2006 and 2020.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of five.

2020

A Scalable Photonic Computer Solving the Subset Sum Problem.

Xiao Yun Xu, Xuan-Lun Huang, Zhan-Ming Li, Jun Gao, Zhi-Qiang Jiao, Yao Wang, Ruo-Jing Ren, H. P. Zhang, Xian-Min Jin

CoRR, 2020

2015

Design and Implementation of an FPGA-Based Data/Timing Formatter.

Yu-Yi Chen, Jiun-Lang Huang, Terry Kuo, Xuan-Lun Huang

J. Electron. Test., 2015

2014

FPGA-Based Subset Sum Delay Lines.

Chung-Yun Wang, Yu-Yi Chen, Jiun-Lang Huang, Xuan-Lun Huang

Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013

A 58.9-dB ACR, 85.5-dB SBA, 5-26-MHz Configurable-Bandwidth, Charge-Domain Filter in 65-nm CMOS.

Ming-Feng Huang, Ming-Ching Kuo, Tzu-Yi Yang, Xuan-Lun Huang

IEEE J. Solid State Circuits, 2013

An IDDQ-based source driver IC design-for-test technique.

S.-S. Lin, C.-L. Kao, Jiun-Lang Huang, C.-C. Lee, Xuan-Lun Huang

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

A mutual characterization based SAR ADC self-testing technique.

H.-J. Lin, Xuan-Lun Huang, Jiun-Lang Huang

Proceedings of the 18th IEEE European Test Symposium, 2013

2012

An MCT-Based Bit-Weight Extraction Technique for Embedded SAR ADC Testing and Calibration.

Xuan-Lun Huang, Jiun-Lang Huang, Hung-I Chen, Chang-Yu Chen, Tseng Kuo-Tsai, Ming-Feng Huang, Yung-Fa Chou, Ding-Ming Kwai

J. Electron. Test., 2012

A Built-In Characterization Technique for 1-Bit/Stage Pipelined ADC.

Y.-H. Chou, Jiun-Lang Huang, Xuan-Lun Huang

Proceedings of the 21st IEEE Asian Test Symposium, 2012

2011

ADC/DAC Loopback Linearity Testing by DAC Output Offsetting and Scaling.

Xuan-Lun Huang, Jiun-Lang Huang

IEEE Trans. Very Large Scale Integr. Syst., 2011

Histogram-Based Calibration of Capacitor Mismatch and Comparator Offset for 1-Bit/Stage Pipelined ADCs.

Xuan-Lun Huang, Ping-Ying Kang, Yuan-Chi Yu, Jiun-Lang Huang

J. Electron. Test., 2011

A Pre- and Post-bond Self-Testing and Calibration Methodology for SAR ADC Array in 3-D CMOS Imager.

Xuan-Lun Huang, Ping-Ying Kang, Jiun-Lang Huang, Yung-Fa Chou, Yung-Pin Lee, Ding-Ming Kwai

Proceedings of the 16th European Test Symposium, 2011

A self-testing and calibration method for embedded successive approximation register ADC.

Xuan-Lun Huang, Ping-Ying Kang, Hsiu-Ming Chang, Jiun-Lang Huang, Yung-Fa Chou, Yung-Pin Lee, Ding-Ming Kwai, Cheng-Wen Wu

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010

An ADC/DAC loopback testing methodology by DAC output offsetting and scaling.

Xuan-Lun Huang, Jiun-Lang Huang

Proceedings of the 28th IEEE VLSI Test Symposium, 2010

A robust ADC code hit counting technique.

Jiun-Lang Huang, Kuo-Yu Chou, Ming-Huan Lu, Xuan-Lun Huang

Proceedings of the Design, Automation and Test in Europe, 2010

2009

An On-Chip Integrator Leakage Characterization Technique and Its Application to Switched Capacitor Circuits Testing.

Chen-Yuan Yang, Xuan-Lun Huang, Jiun-Lang Huang

Proceedings of the Eighteentgh Asian Test Symposium, 2009

Diagnosing integrator leakage of single-bit first-order DeltaSigma modulator using DC input.

Xuan-Lun Huang, Chen-Yuan Yang, Jiun-Lang Huang

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2006

A routability constrained scan chain ordering technique for test power reduction.

Xuan-Lun Huang, Jiun-Lang Huang

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006