Xu Han

According to our database, Xu Han authored at least 10 papers between 2010 and 2014.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2014

Out-of-Order Parallel Discrete Event Simulation for Transaction Level Models.

Weiwei Chen, Xu Han, Che-Wei Chang, Guantao Liu, Rainer Dömer

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

May-happen-in-parallel analysis based on segment graphs for safe ESL models.

Weiwei Chen, Xu Han, Rainer Dömer

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013

Advances in Parallel Discrete Event Simulation for Electronic System-Level Design.

Weiwei Chen, Xu Han, Che-Wei Chang, Rainer Dömer

IEEE Des. Test, 2013

Designer-in-the-loop recoding of ESL models using static parallel access conflict analysis.

Xu Han, Weiwei Chen, Rainer Dömer

Proceedings of the International Workshop on Software and Compilers for Embedded Systems, 2013

2012

Eliminating race conditions in system-level models by using parallel simulation infrastructure.

Weiwei Chen, Che-Wei Chang, Xu Han, Rainer Dömer

Proceedings of the 2012 IEEE International High Level Design Validation and Test Workshop, 2012

Out-of-order parallel simulation for ESL design.

Weiwei Chen, Xu Han, Rainer Dömer

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Parallel discrete event simulation of Transaction Level Models.

Rainer Dömer, Weiwei Chen, Xu Han

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011

Multicore Simulation of Transaction-Level Models Using the SoC Environment.

Weiwei Chen, Xu Han, Rainer Dömer

IEEE Des. Test Comput., 2011

Multi-core parallel simulation of System-level Description Languages.

Rainer Dömer, Weiwei Chen, Xu Han, Andreas Gerstlauer

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010

ESL design and multi-core validation using the System-on-Chip Environment.

Weiwei Chen, Xu Han, Rainer Dömer

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2010