Xu Guo

Affiliations:
  • Virginia Tech, Blacksburg, VA, USA


According to our database1, Xu Guo authored at least 12 papers between 2008 and 2013.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2013
Design and benchmarking of an ASIC with five SHA-3 finalist candidates.
Microprocess. Microsystems, 2013

Study of ASIC technology impact factors on performance evaluation of SHA-3 candidates.
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

2012
ASIC implementations of five SHA-3 finalists.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
Pre-silicon Characterization of NIST SHA-3 Final Round Candidates.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

Data-oriented performance analysis of SHA-3 candidates on FPGA accelerated computers.
Proceedings of the Design, Automation and Test in Europe, 2011

2010
Optimized System-on-Chip Integration of a Programmable ECC Coprocessor.
ACM Trans. Reconfigurable Technol. Syst., 2010

On The Impact of Target Technology in SHA-3 Hardware Benchmark Rankings.
IACR Cryptol. ePrint Arch., 2010

State-of-the-art of Secure ECC Implementations: A Survey on Known Side-channel Attacks and Countermeasures.
Proceedings of the HOST 2010, 2010

2009
Optimizing the HW/SW boundary of an ECC SoC design using control hierarchy and distributed storage.
Proceedings of the Design, Automation and Test in Europe, 2009

Programmable and Parallel ECC Coprocessor Architecture: Tradeoffs between Area, Speed and Security.
Proceedings of the Cryptographic Hardware and Embedded Systems, 2009

Optimizing the Control Hierarchy of an ECC Coprocessor Design on an FPGA Based SoC Platform.
Proceedings of the Reconfigurable Computing: Architectures, 2009

2008
Energy and Performance Evaluation of an FPGA-Based SoC Platform with AES and PRESENT Coprocessors.
Proceedings of the Embedded Computer Systems: Architectures, 2008


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