A Self Bias-flip Piezoelectric Energy Harvester Array without External Energy Reservoirs achieving 488% Improvement with 4-Ratio Switched-PEH DC-DC Converter.

[BibT_eX]

[DOI]

Zhen Li

Zhiyuan Chen

Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

2022

An Enhanced Start-up Circuit Eliminating All Trojan States in Self-biased Reference Generators.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A Synthesis Friendly Dynamic Amplifier with Fuzzy-Logic Piecewise-Linear Calibration.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A Cross Regulation Reduced Multi-Output and Multi-VCR Piezoelectric Energy Harvesting System Using Shared Capacitors.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A Fully Synthesizable Dynamic Latched Comparator with Reduced Kickback Noise.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

An Improved Multi-Objective Optimization Framework for Soft-Error Immune Circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

2021

General Efficient TMR for Combinational Circuit Hardening Against Soft Errors and Improved Multi-Objective Optimization Framework.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Radiation Hardened 12T SRAM With Crossbar-Based Peripheral Circuit in 28nm CMOS Technology.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

A 28 nm, 397 μW real-time dynamic gesture recognition chip based on RISC-V processor.

[BibT_eX]

[DOI]

Microelectron. J., 2021

An energy-efficient crypto-extension design for RISC-V.

[BibT_eX]

[DOI]

Microelectron. J., 2021

Synthesizable lead-lag quantization technique for digital VCO-based ΔΣ ADC.

[BibT_eX]

[DOI]

Microelectron. J., 2021

A Synthesizable 0.0060mm<sup>2</sup> VCO-Based Delta Sigma Modulator with Digital Tri-level Feedback Scheme.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021

A High-Efficient and Configurable Hardware Accelerator for Convolutional Neural Network.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on ASIC, 2021

A 0.9V Supply 12.5Gb/s LVDS Receiver in 28nm CMOS Process.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on ASIC, 2021

2020

Radiation-Hardened 0.3-0.9-V Voltage-Scalable 14T SRAM and Peripheral Circuit in 28-nm Technology for Space Applications.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2020

VPQC: A Domain-Specific Vector Processor for Post-Quantum Cryptography Based on RISC-V Architecture.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2020

A Robust Hardened Latch Featuring Tolerance to Double-Node-Upset in 28nm CMOS for Spaceborne Application.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2020

A Synthesis Friendly VCO-Based Delta-Sigma ADC with Process Variation Tolerance.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Design Methodology of Clock Polarity Inversion Technique for Frequency Dividers.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Exploring a Bayesian Optimization Framework Compatible with Digital Standard Flow for Soft-Error-Tolerant Circuit.

[BibT_eX]

[DOI]

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019

A 24-bit sigma-delta ADC with configurable chopping scheme.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2019

2016

Bit-Interleaving-Enabled 8T SRAM With Shared Data-Aware Write and Reference-Based Sense Amplifier.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2016

Subthreshold Level Shifter With Self-Controlled Current Limiter by Detecting Output Error.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2016

Analysis and improvement of ramp gain error in single-ramp single-slope ADCs for CMOS image sensors.

[BibT_eX]

[DOI]

Xu Cheng

Xiaoyang Zeng

Qi Feng

Microelectron. J., 2016

2015

Design and Analysis of Highly Energy/Area-Efficient Multiported Register Files With Read Word-Line Sharing Strategy in 65-nm CMOS Process.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

Non-binary digital calibration for split-capacitor DAC in SAR ADC.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2015

2014

A 16-Core Processor With Shared-Memory and Message-Passing Communications.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

An area-efficient dual replica-bitline delay technique for process-variation-tolerant low voltage SRAM sense amplifier timing.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2014

2013

A 960 μW 10-bit 70-MS/s SAR ADC with an energy-efficient capacitor-switching scheme.

[BibT_eX]

[DOI]

Yue Wu

Xu Cheng

Xiaoyang Zeng

Microelectron. J., 2013

A split-capacitor vcm-based capacitor-switching scheme for low-power SAR ADCs.

[BibT_eX]

[DOI]

Yue Wu

Xu Cheng

Xiaoyang Zeng

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A highly energy-efficient compressed sensing encoder with robust subthreshold clockless pipeline for wireless BANs.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE Biomedical Circuits and Systems Conference (BioCAS), Rotterdam, The Netherlands, October 31, 2013

A 1.8-V 14-bit inverter-based incremental ΣΔ ADC for CMOS image sensor.

[BibT_eX]

[DOI]

Proceedings of the IEEE 10th International Conference on ASIC, 2013

An extensible and real-time compressive sensing reconstruction hardware for WBANs using OMP.

[BibT_eX]

[DOI]

Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012

A 64×32bit 4-read 2-write low power and area efficient register file in 65nm CMOS.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2012

2011

A low power 1.0 GHz VCO in 65nm-CMOS LP-process.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

A low power 10-bit 100-MS/s SAR ADC in 65nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

A multi-mode 1-V DAC+filter in 65-nm CMOS for reconfigurable (GSM, TD-SCDMA and WCDMA) transmitters.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

Modeling of a double-sampling switched-capacitor bandpass delta-sigma modulator for multi-standard applications.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

Xu Cheng

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