Xu Cheng

Orcid: 0000-0002-5544-8852

Affiliations:

Peking University, Microprocessor Research and Development Center, Beijing, China

According to our database¹, Xu Cheng authored at least 75 papers between 2005 and 2024.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

Legend:

Book

In proceedings

Article

PhD thesis

Dataset

Other

Bibliography

2024

Oblivious Demand Paging with Ring ORAM in RISC-V Trusted Execution Environments.

[BibT_eX]

[DOI]

Proceedings of the 27th International Conference on Computer Supported Cooperative Work in Design, 2024

2023

A High-Coverage and Efficient Instruction-Level Testing Approach for x86 Processors.

[BibT_eX]

[DOI]

IEEE Trans. Computers, November, 2023

Information Leakage Attacks Exploiting Cache Replacement in Commercial Processors.

[BibT_eX]

[DOI]

Yujie Cui

Hongwei Cui

Xu Cheng

IEEE Trans. Computers, September, 2023

FlexPointer: Fast Address Translation Based on Range TLB and Tagged Pointers.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., June, 2023

Secure Speculation via Speculative Secret Flow Tracking.

[BibT_eX]

[DOI]

Hongwei Cui

Chun Yang

Xu Cheng

J. Comput. Sci. Technol., April, 2023

High-Speed and Energy-Efficient Single-Port Content Addressable Memory to Achieve Dual-Port Operation.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

A Hardware-Software Cooperative Interval-Replaying for FPGA-based Architecture Evaluation.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Detecting and Mitigating Cache Side Channel Threats on Intel SGX.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on Computer Supported Cooperative Work in Design, 2023

MBAPIS: Multi-Level Behavior Analysis Guided Program Interval Selection for Microarchitecture Studies.

[BibT_eX]

[DOI]

Proceedings of the 32nd International Conference on Parallel Architectures and Compilation Techniques, 2023

2022

In-depth Testing of x86 Instruction Disassemblers with Feedback Controlled DFS Algorithm.

[BibT_eX]

[DOI]

Proceedings of the IEEE 40th International Conference on Computer Design, 2022

Abusing Cache Line Dirty States to Leak Information in Commercial Processors.

[BibT_eX]

[DOI]

Yujie Cui

Chun Yang

Xu Cheng

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022

2021

Abusing Cache Line Dirty States to Leak Information in Commercial Processors.

[BibT_eX]

[DOI]

Yujie Cui

Xu Cheng

CoRR, 2021

Differential Testing of x86 Instruction Decoders with Instruction Operand Inferring Algorithm.

[BibT_eX]

[DOI]

Proceedings of the 39th IEEE International Conference on Computer Design, 2021

MetaTableLite: An Efficient Metadata Management Scheme for Tagged-Pointer-Based Spatial Safety.

[BibT_eX]

[DOI]

Proceedings of the 39th IEEE International Conference on Computer Design, 2021

2020

S3Library: Automatically Eliminating C/C++ Buffer Overflow using Compatible Safer Libraries.

[BibT_eX]

[DOI]

CoRR, 2020

DangKiller: Eliminating Dangling Pointers Efficiently via Implicit Identifier.

[BibT_eX]

[DOI]

CoRR, 2020

SMA: Eliminate Memory Spatial Errors via Saturation Memory Access.

[BibT_eX]

[DOI]

CoRR, 2020

2019

Coalesced TLB to Exploit Diverse Contiguity of Memory Mapping.

[BibT_eX]

[DOI]

CoRR, 2019

2017

Content Look-Aside Buffer for Redundancy-Free Virtual Disk I/O and Caching.

[BibT_eX]

[DOI]

Chun Yang

Xianhua Liu

Xu Cheng

Proceedings of the 13th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments, 2017

Prediction of distribution network malfunction based on meteorological factors.

[BibT_eX]

[DOI]

Proceedings of the 13th International Conference on Natural Computation, 2017

Understanding the I/O Behavior of Desktop Applications in Virtualization.

[BibT_eX]

[DOI]

Yan Sui

Chun Yang

Xu Cheng

Proceedings of the Computing Frontiers Conference, 2017

Locality-aware bank partitioning for shared DRAM MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

A Staged Memory Resource Management Method for CMP systems.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE International Conference on Application-specific Systems, 2017

2016

MFAP: Fair Allocation between fully backlogged and non-fully backlogged applications.

[BibT_eX]

[DOI]

Proceedings of the 34th IEEE International Conference on Computer Design, 2016

vSIP: virtual scheduler for interactive performance.

[BibT_eX]

[DOI]

Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

2015

An Energy-Efficient Branch Prediction with Grouped Global History.

[BibT_eX]

[DOI]

Proceedings of the 44th International Conference on Parallel Processing, 2015

Exploration of the Relationship Between Just-in-Time Compilation Policy and Number of Cores.

[BibT_eX]

[DOI]

Proceedings of the Algorithms and Architectures for Parallel Processing, 2015

2014

Retention Benefit Based Intelligent Cache Replacement.

[BibT_eX]

[DOI]

Lingda Li

Junlin Lu

Xu Cheng

J. Comput. Sci. Technol., 2014

SPTU: Improving Dynamic Binary Translation through Software Prediction with Target Updating.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Systems and Storage, 2014

Block value based insertion policy for high performance last-level caches.

[BibT_eX]

[DOI]

Lingda Li

Junlin Lu

Xu Cheng

Proceedings of the 2014 International Conference on Supercomputing, 2014

Improving system throughput and fairness simultaneously in shared memory CMP systems via Dynamic Bank Partitioning.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

DTT: program structure-aware indirect branch optimization via direct-TPC-table in DBT system.

[BibT_eX]

[DOI]

Proceedings of the Computing Frontiers Conference, CF'14, 2014

2013

Page policy control with memory partitioning for DRAM performance and power efficiency.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

An energy-efficient branch prediction technique via global-history noise reduction.

[BibT_eX]

[DOI]

Zichao Xie

Dong Tong

Xu Cheng

Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

2012

SWIP Prediction: Complexity-Effective Indirect-Branch Prediction Using Pointers.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2012

Affinity-aware DMA buffer management for reducing off-chip memory access.

[BibT_eX]

[DOI]

Proceedings of the ACM Symposium on Applied Computing, 2012

Reducing last level cache pollution through OS-level software-controlled region-based partitioning.

[BibT_eX]

[DOI]

Proceedings of the ACM Symposium on Applied Computing, 2012

CVP: an energy-efficient indirect branch prediction with compiler-guided value pattern.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Supercomputing, 2012

Improving inclusive cache performance with two-level eviction priority.

[BibT_eX]

[DOI]

Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Energy-efficient branch prediction with Compiler-guided History Stack.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

An integrated and automated memory optimization flow for FPGA behavioral synthesis.

[BibT_eX]

[DOI]

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

Optimal bypass monitor for high performance last-level caches.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012

2011

Dynamic Memory Demand Estimating Based on the Guest Operating System Behaviors for Virtual Machines.

[BibT_eX]

[DOI]

Yan Niu

Chun Yang

Xu Cheng

Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2011

TAP prediction: Reusing conditional branch predictor for indirect branches with Target Address Pointers.

[BibT_eX]

[DOI]

Proceedings of the IEEE 29th International Conference on Computer Design, 2011

2010

Research Progress of UniCore CPUs and PKUnity SoCs.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2010

TERA: A FPGA-based trace-driven emulation framework for designing on-chip communication architectures.

[BibT_eX]

[DOI]

Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

Energy efficient management scheme for heterogeneous secondary storage system in mobile computers.

[BibT_eX]

[DOI]

Proceedings of the 2010 ACM Symposium on Applied Computing (SAC), 2010

Bit-level optimization for high-level synthesis and FPGA-based acceleration.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

FPGA prototyping of an amba-based windows-compatible SoC.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

FEMU: a firmware-based emulation framework for SoC verification.

[BibT_eX]

[DOI]

Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis, 2010

A customized design of DRAM controller for on-chip 3D DRAM stacking.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

A 3D SoC design for H.264 application with on-chip DRAM stacking.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on 3D System Integration, 2010

2009

PaS: A Preemption-aware Scheduling Interface for Improving Interactive Performance in Consolidated Virtual Machine Environment.

[BibT_eX]

[DOI]

Yubin Xia

Chun Yang

Xu Cheng

Proceedings of the 15th IEEE International Conference on Parallel and Distributed Systems, 2009

A Heterogeneous Auto-offloading Framework Based on Web Browser for Resource-Constrained Devices.

[BibT_eX]

[DOI]

Proceedings of the Fourth International Conference on Internet and Web Applications and Services, 2009

WHOLE: A low energy I-Cache with separate way history.

[BibT_eX]

[DOI]

Zichao Xie

Dong Tong

Xu Cheng

Proceedings of the 27th International Conference on Computer Design, 2009

Track Down HW Function Faults Using Real SW Invariants.

[BibT_eX]

[DOI]

Proceedings of the CSIE 2009, 2009 WRI World Congress on Computer Science and Information Engineering, March 31, 2009

2008

CASA: A New IFU Architecture for Power-Efficient Instruction Cache and TLB Designs.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2008

Analysis and Enhancement for Interactive-Oriented Virtual Machine Scheduling.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE/IPIP International Conference on Embedded and Ubiquitous Computing (EUC 2008), 2008

Super-K: A SoC for single-chip ultra mobile computer.

[BibT_eX]

[DOI]

Xu Cheng

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007

An Energy-Efficient Instruction Scheduler Design with Two-Level Shelving and Adaptive Banking.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2007

A Fast and Efficient Codec for Multimedia Applications in Wireless Thin-Client Computing.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Symposium on a World of Wireless, 2007

Efficient code size reduction without performance loss.

[BibT_eX]

[DOI]

Xianhua Liu

Jiyu Zhang

Xu Cheng

Proceedings of the 2007 ACM Symposium on Applied Computing (SAC), 2007

Unichos: a full system simulator for thin client platform.

[BibT_eX]

[DOI]

Proceedings of the 2007 ACM Symposium on Applied Computing (SAC), 2007

NISD: A Framework for Automatic Narrow Instruction Set Design.

[BibT_eX]

[DOI]

Xianhua Liu

Jiyu Zhang

Xu Cheng

Proceedings of the Embedded Software and Systems, [Third] International Conference, 2007

Reuse Distance Based Cache Leakage Control.

[BibT_eX]

[DOI]

Proceedings of the High Performance Computing, 2007

A Fast Lossless Codec of Continuous-Tone Images for Thin Client Computing.

[BibT_eX]

[DOI]

Proceedings of the 2007 Data Compression Conference (DCC 2007), 2007

Clock domain crossing fault model and coverage metric for validation of SoC design.

[BibT_eX]

[DOI]

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

A Retargetable Software Timing Analyzer Using Architecture Description Language.

[BibT_eX]

[DOI]

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

GISP: A Transparent Superpage Support Framework for Linux.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Application-Specific Systems, 2007

An Efficient SSA-Based Algorithm for Complete Global Value Numbering.

[BibT_eX]

[DOI]

Jiu-Tao Nie

Xu Cheng

Proceedings of the Programming Languages and Systems, 5th Asian Symposium, 2007

2006

A Low Complexity MPEG Video Decoder with Arbitrary Downscaling Capability.

[BibT_eX]

[DOI]

Shu Shi

Feng Liu

Xu Cheng

Proceedings of the 2006 4th Workshop on Embedded Systems for Real-Time Multimedia, 2006

2005

Lower-bound estimation for multi-bitwidth scheduling.

[BibT_eX]

[DOI]

Junjuan Xu

Jason Cong

Xu Cheng

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Non-interleaving architecture for hardware implementation of modular multiplication.

[BibT_eX]

[DOI]

Qiang Liu

Dong Tong

Xu Cheng

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

BluePower - A New Distributed Multihop Scatternet Formation Protocol for Bluetooth Networks.

[BibT_eX]

[DOI]

Proceedings of the 34th International Conference on Parallel Processing (ICPP 2005), 2005

Bitwidth-aware scheduling and binding in high-level synthesis.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Xu Cheng

Timeline

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