Xizhu Peng

Orcid: 0000-0003-0187-1601

According to our database1, Xizhu Peng authored at least 22 papers between 2014 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
A New Artificial Neural Network-Based Calibration Mechanism for ADCs: A Time-Interleaved ADC Case Study.
IEEE Trans. Very Large Scale Integr. Syst., July, 2024

A Novel Calibration Algorithm for ADCs Based on Inverse Mapping by Neural Network.
IEEE Trans. Circuits Syst. II Express Briefs, July, 2024

Digital Background Calibration Techniques for Interstage Gain Error and Nonlinearity in Pipelined ADCs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

Evolution Strategy and Controlled Residual Convolutional Neural Networks for ADC Calibration in the Absence of Ground Truth.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2023
A Novel Two-Stage Timing Mismatch Calibration Technique for Time-Interleaved ADCs.
IEEE Trans. Very Large Scale Integr. Syst., June, 2023

A Neural Network Based Calibration Technique for TI-ADCs with Derivative Information.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

A Convolutional Neural Network Based Calibration Scheme for Pipelined ADC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

A Sinusoidal Fitting-based Digital Foreground Calibration Technique for Pipelined ADC.
Proceedings of the 15th IEEE International Conference on ASIC, 2023

2022
DBP: Distributed Power Budgeting for Many-Core Systems in Dark Silicon.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

2021
A Three-Stage Comparator and Its Modified Version With Fast Speed and Low Kickback.
IEEE Trans. Very Large Scale Integr. Syst., 2021

A Timing Mismatch Background Calibration Algorithm With Improved Accuracy.
IEEE Trans. Very Large Scale Integr. Syst., 2021

A Fully Dynamic Low-Power Wideband Time-Interleaved Noise-Shaping SAR ADC.
IEEE J. Solid State Circuits, 2021

A Back-Gate-Input Clocked Comparator with Improved Speed and Reduced Noise in 22-nm SOI CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

A Bootstrapped Switch with Accelerated Rising Speed and Reduced On-Resistance.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

A Timing Mismatch Background Calibration Technique with High-Precision Skew Estimation.
Proceedings of the 14th IEEE International Conference on ASIC, 2021

2020
Low-Power, Low-Noise Edge-Race Comparator for SAR ADCs.
IEEE Trans. Very Large Scale Integr. Syst., 2020

A 8.2-pW 2.4-pA Current Reference Operating at 0.5 V With No Amplifiers or Resistors.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

A 7.6b ENOB, 16× Gain, 360mVpp Output Swing, Open-Loop Charge Steering Amplifier.
IEEE Access, 2020

2019
A Low-Power Low-Cost On-Chip Digital Background Calibration for Pipelined ADCs.
IEEE Trans. Very Large Scale Integr. Syst., 2019

2018
A 0.5-nW 29ppm/°C Voltage Reference Circuit.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

2017
A low-power on-chip calibration technique for pipelined ADCs.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

2014
Design and High-Speed Demonstration of Single-Flux-Quantum Bit-Serial Floating-Point Multipliers Using a 10kA/cm<sup>2</sup> Nb Process.
IEICE Trans. Electron., 2014


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