Xiyuan Tang
Orcid: 0000-0003-2181-9042
According to our database1,
Xiyuan Tang
authored at least 91 papers
between 2015 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
A 0.004-mm<sup>2</sup> 200-MS/s Pipelined SAR ADC With kT/C Noise Cancellation and Robust Ring-Amp.
IEEE J. Solid State Circuits, July, 2024
A 16.38TOPS and 4.55POPS/W SRAM Computing-in-Memory Macro for Signed Operands Computation and Batch Normalization Implementation.
IEEE Trans. Circuits Syst. I Regul. Pap., April, 2024
A 4-bit Calibration-Free Computing-In-Memory Macro With 3T1C Current-Programed Dynamic-Cascode Multi-Level-Cell eDRAM.
IEEE J. Solid State Circuits, March, 2024
LayoutCopilot: An LLM-powered Multi-agent Collaborative Framework for Interactive Analog Layout Design.
CoRR, 2024
EasyACIM: An End-to-End Automated Analog CIM with Synthesizable Architecture and Agile Design Space Exploration.
CoRR, 2024
30.5 A Variation-Tolerant In-eDRAM Continuous-Time Ising Machine Featuring 15-Level Coefficients and Leaked Negative-Feedback Annealing.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
SAGERoute 2.0: Hierarchical Analog and Mixed Signal Routing Considering Versatile Routing Scenarios.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
A 181.8dB FoMs Zoom Capacitance-to-Digital Converter with kT/C Noise Cancellation and Dead Band Operation.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024
MixCIM: A Hybrid-Cell-Based Computing-in-Memory Macro with Less-Data-Movement and Activation-Memory-Reuse for Depthwise Separable Neural Networks.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024
A 28nm 128TFLOPS/W Computing-In-Memory Engine Supporting One-Shot Floating-Point NN Inference and On-Device Fine-Tuning for Edge AI.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024
2023
A Bandwidth-Adaptive Pipelined SAR ADC With Three-Stage Cascoded Floating Inverter Amplifier.
IEEE J. Solid State Circuits, September, 2023
A 28 nm 16 Kb Bit-Scalable Charge-Domain Transpose 6T SRAM In-Memory Computing Macro.
IEEE Trans. Circuits Syst. I Regul. Pap., May, 2023
IEEE J. Solid State Circuits, May, 2023
IEEE Trans. Circuits Syst. I Regul. Pap., 2023
A 150kHz-BW 15-ENOB Incremental Zoom ADC with Skipped Sampling and Single Buffer Embedded Noise-Shaping SAR Quantizer.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A 28nm 38-to-102-TOPS/W 8b Multiply-Less Approximate Digital SRAM Compute-In-Memory Macro for Neural-Network Inference.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
SAGERoute: Synergistic Analog Routing Considering Geometric and Electrical Constraints with Manual Design Compatibility.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
An 80.2-to-89.1dB-SNDR 24k-to-200kHz-BW VCO-Based Synthesized ?S ADC with 105dB SFDR in 28-nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
A Calibration-Free 15-level/Cell eDRAM Computing-in-Memory Macro with 3T1C Current-Programmed Dynamic-Cascoded MLC achieving 233-to-304-TOPS/W 4b MAC.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
A 9.7fJ/Conv.-Step Capacitive Sensor Readout Circuit with Incremental Zoomed Time Domain Quantization.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
2022
A 65 nm 73 kb SRAM-Based Computing-In-Memory Macro With Dynamic-Sparsity Controlling.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
A 0.004mm<sup>2</sup> 200MS/S Pipelined SAR ADC with kT/C Noise Cancellation and Robust Ring-Amp.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
A 0.014mm<sup>2</sup> 10kHz-BW Zoom-Incremental-Counting ADC Achieving 103dB SNDR and 100dB Full-Scale CMRR.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
A 0.37mm<sup>2</sup> 250kHz-BW 95dB-SNDR CTDSM with Low-Cost 2<sup>nd</sup>-order Vector-Quantizer DEM.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022
A Vector Pair Based DWA Algorithm for Linearity Enhancement of CDACs in the NS-SAR ADC.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022
2021
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
A 13.8-ENOB Fully Dynamic Third-Order Noise-Shaping SAR ADC in a Single-Amplifier EF-CIFF Structure With Hardware-Reusing kT/C Noise Cancellation.
IEEE J. Solid State Circuits, 2021
A 74.5-dB Dynamic Range 10-MHz BW CT-ΔΣ ADC With Distributed-Input VCO and Embedded Capacitive-π Network in 40-nm CMOS.
IEEE J. Solid State Circuits, 2021
A 90-dB-SNDR Calibration-Free Fully Passive Noise-Shaping SAR ADC With 4× Passive Gain and Second-Order DAC Mismatch Error Shaping.
IEEE J. Solid State Circuits, 2021
A 77.1-dB-SNDR 6.25-MHz-BW Pipeline SAR ADC With Enhanced Interstage Gain Error Shaping and Quantization Noise Shaping.
IEEE J. Solid State Circuits, 2021
MAGICAL: An Open- Source Fully Automated Analog IC Layout System from Netlist to GDSII.
IEEE Des. Test, 2021
A 0.4-to-40MS/s 75.7dB-SNDR Fully Dynamic Event-Driven Pipelined ADC with 3-Stage Cascoded Floating Inverter Amplifier.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
27.1 A 250kHz-BW 93dB-SNDR 4<sup>th</sup>-Order Noise-Shaping SAR Using Capacitor Stacking and Dynamic Buffering.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
Universal Symmetry Constraint Extraction for Analog and Mixed-Signal Circuits with Graph Neural Networks.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021
MAGICAL 1.0: An Open-Source Fully-Automated AMS Layout Synthesis Framework Verified With a 40-nm 1GS/s Δ∑ ADC.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021
A 16Kb Transpose 6T SRAM In-Memory-Computing Macro based on Robust Charge-Domain Computing.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
2020
A Second-Order Purely VCO-Based CT ΔΣ ADC Using a Modified DPLL Structure in 40-nm CMOS.
IEEE J. Solid State Circuits, 2020
A 0.025-mm<sup>2</sup> 0.8-V 78.5-dB SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL- ΔΣ M Structure.
IEEE J. Solid State Circuits, 2020
A Fractional-<i>N</i> PLL With Space-Time Averaging for Quantization Noise Reduction.
IEEE J. Solid State Circuits, 2020
A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier.
IEEE J. Solid State Circuits, 2020
IEEE J. Solid State Circuits, 2020
IEEE J. Solid State Circuits, 2020
IEEE J. Solid State Circuits, 2020
IEEE J. Solid State Circuits, 2020
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
9.5 A 13.5b-ENOB Second-Order Noise-Shaping SAR with PVT-Robust Closed-Loop Dynamic Amplifier.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
9.3 A 40kHz-BW 90dB-SNDR Noise-Shaping SAR with 4× Passive Gain and 2<sup>nd</sup>-Order Mismatch Error Shaping.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
Towards Decrypting the Art of Analog Layout: Placement Quality Prediction via Transfer Learning.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Closing the Design Loop: Bayesian Optimization Assisted Hierarchical Analog Layout Synthesis.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
A 77.1-dB 6.25-MHz-BW Pipeline SAR ADC with Enhanced Interstage Gain Error Shaping and Quantization Error Shaping.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2020
S<sup>3</sup>DET: Detecting System Symmetry Constraints for Analog Circuits with Graph Similarity.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
2019
A 10-b 600-MS/s 2-Way Time-Interleaved SAR ADC With Mean Absolute Deviation-Based Background Timing-Skew Calibration.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
IEEE J. Solid State Circuits, 2019
IEICE Trans. Electron., 2019
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
A 0.01mm<sup>2</sup> 25µW 2MS/s 74dB-SNDR Continuous-Time Pipelined-SAR ADC with 120fF Input Capacitor.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
Proceedings of the International Conference on Computer-Aided Design, 2019
MAGICAL: Toward Fully Automated Analog IC Layout Leveraging Human and Machine Intelligence: Invited Paper.
Proceedings of the International Conference on Computer-Aided Design, 2019
WellGAN: Generative-Adversarial-Network-Guided Well Generation for Analog/Mixed-Signal Circuit Layout.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
A 0.025-mm<sup>2</sup> 0.8-V 78.5dB-SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL-ΔΣM Structure.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
S<sup>2</sup>-PM: semi-supervised learning for efficient performance modeling of analog and mixed signal circuits.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019
2018
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
2017
IEEE Trans. Circuits Syst. II Express Briefs, 2017
A 10-b 800-MS/s Time-Interleaved SAR ADC With Fast Variance-Based Timing-Skew Calibration.
IEEE J. Solid State Circuits, 2017
A 0.7-V 0.6-µW 100-kS/s Low-Power SAR ADC With Statistical Estimation-Based Noise Reduction.
IEEE J. Solid State Circuits, 2017
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017
2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016
2015
A 0.04-mm<sup>2</sup> 0.9-mW 71-dB SNDR distributed modular AS ADC with VCO-based integrator and digital DAC calibration.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
A 10.5-b ENOB 645 nW 100kS/s SAR ADC with statistical estimation based noise reduction.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015