Xiyuan Tang

According to our database, Xiyuan Tang authored at least 93 papers between 2015 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

CASCADE: A Framework for CNN Accelerator Synthesis With Concatenation and Refreshing Dataflow.

Qingyu Guo, Haoyang Luo, Meng Li, Xiyuan Tang, Yuan Wang

IEEE Trans. Circuits Syst. I Regul. Pap., November, 2024

A 0.004-mm² 200-MS/s Pipelined SAR ADC With kT/C Noise Cancellation and Robust Ring-Amp.

Mingtao Zhan, Lu Jie, Xiyuan Tang, Yi Zhong, Nan Sun

IEEE J. Solid State Circuits, July, 2024

A 16.38TOPS and 4.55POPS/W SRAM Computing-in-Memory Macro for Signed Operands Computation and Batch Normalization Implementation.

Xin Qiao, Qingyu Guo, Xiyuan Tang, Jiahao Song, Renjie Wei, Meng Li, Runsheng Wang, Yuan Wang

IEEE Trans. Circuits Syst. I Regul. Pap., April, 2024

A 4-bit Calibration-Free Computing-In-Memory Macro With 3T1C Current-Programed Dynamic-Cascode Multi-Level-Cell eDRAM.

Jiahao Song, Xiyuan Tang, Haoyang Luo, Haoyi Zhang, Xin Qiao, Zixuan Sun, Xiangxing Yang, Zihan Wu, Yuan Wang, Runsheng Wang, Ru Huang

IEEE J. Solid State Circuits, March, 2024

LayoutCopilot: An LLM-powered Multi-agent Collaborative Framework for Interactive Analog Layout Design.

Bingyang Liu, Haoyi Zhang, Xiaohan Gao, Zichen Kong, Xiyuan Tang, Yibo Lin, Runsheng Wang, Ru Huang

CoRR, 2024

30.5 A Variation-Tolerant In-eDRAM Continuous-Time Ising Machine Featuring 15-Level Coefficients and Leaked Negative-Feedback Annealing.

Jiahao Song, Zihan Wu, Xiyuan Tang, Bocheng Xu, Haoyang Luo, Youming Yang, Yuan Wang, Runsheng Wang, Ru Huang

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

SAGERoute 2.0: Hierarchical Analog and Mixed Signal Routing Considering Versatile Routing Scenarios.

Haoyi Zhang, Xiaohan Gao, Zilong Shen, Jiahao Song, Xiaoxu Cheng, Xiyuan Tang, Yibo Lin, Runsheng Wang, Ru Huang

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

EasyACIM: An End-to-End Automated Analog CIM with Synthesizable Architecture and Agile Design Space Exploration.

Haoyi Zhang, Jiahao Song, Xiaohan Gao, Xiyuan Tang, Yibo Lin, Runsheng Wang, Ru Huang

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

PVTSizing: A TuRBO-RL-Based Batch-Sampling Optimization Framework for PVT-Robust Analog Circuit Synthesis.

Zichen Kong, Xiyuan Tang, Wei Shi, Yiheng Du, Yibo Lin, Yuan Wang

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

A 181.8dB FoMs Zoom Capacitance-to-Digital Converter with kT/C Noise Cancellation and Dead Band Operation.

Zilong Shen, Jiaiun Tang, Haoyang Luo, Zhongyi Wu, Zongnan Wang, Xing Zhang, Xiyuan Tang, Yuan Wang

Proceedings of the IEEE Custom Integrated Circuits Conference, 2024

MixCIM: A Hybrid-Cell-Based Computing-in-Memory Macro with Less-Data-Movement and Activation-Memory-Reuse for Depthwise Separable Neural Networks.

Xin Qiao, Jiahao Song, Youming Yang, Renjie Wei, Xiyuan Tang, Meng Li, Runsheng Wang, Yuan Wang

Proceedings of the IEEE Custom Integrated Circuits Conference, 2024

A 28nm 128TFLOPS/W Computing-In-Memory Engine Supporting One-Shot Floating-Point NN Inference and On-Device Fine-Tuning for Edge AI.

Haikang Diao, Haoyang Luo, Jiahao Song, Bocheng Xu, Runsheng Wang, Yuan Wang, Xiyuan Tang

Proceedings of the IEEE Custom Integrated Circuits Conference, 2024

2023

A Bandwidth-Adaptive Pipelined SAR ADC With Three-Stage Cascoded Floating Inverter Amplifier.

Xiyuan Tang, Xiangxing Yang, Jiaxin Liu, Zongnan Wang, Wei Shi, David Z. Pan, Nan Sun

IEEE J. Solid State Circuits, September, 2023

A 28 nm 16 Kb Bit-Scalable Charge-Domain Transpose 6T SRAM In-Memory Computing Macro.

Jiahao Song, Xiyuan Tang, Xin Qiao, Yuan Wang, Runsheng Wang, Ru Huang

IEEE Trans. Circuits Syst. I Regul. Pap., May, 2023

An In-Memory-Computing Charge-Domain Ternary CNN Classifier.

Xiangxing Yang, Keren Zhu, Xiyuan Tang, Meizhi Wang, Mingtao Zhan, Nanshu Lu, Jaydeep P. Kulkarni, David Z. Pan, Yongpan Liu, Nan Sun

IEEE J. Solid State Circuits, May, 2023

A Power-Efficient 13-Tap FIR Filter and an IIR Filter Embedded in a 10-Bit SAR ADC.

Xin Xin, Linxiao Shen, Xiyuan Tang, Yi Shen, Jueping Cai, Xingyuan Tong, Nan Sun

IEEE Trans. Circuits Syst. I Regul. Pap., 2023

A 150kHz-BW 15-ENOB Incremental Zoom ADC with Skipped Sampling and Single Buffer Embedded Noise-Shaping SAR Quantizer.

Zongnan Wang, Lu Jie, Zichen Kong, Mingtao Zhan, Yi Zhong, Yuan Wang, Xiyuan Tang

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

A 28nm 38-to-102-TOPS/W 8b Multiply-Less Approximate Digital SRAM Compute-In-Memory Macro for Neural-Network Inference.

Yifan He, Haikang Diao, Chen Tang, Wenbin Jia, Xiyuan Tang, Yuan Wang, Jinshan Yue, Xueqing Li, Huazhong Yang, Hongyang Jia, Yongpan Liu

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

An NS-SAR ADC with Full-bit High-order Mismatch Shaped CDAC.

Xiao Han, Xiyuan Tang, Zibo Ma, Xinzi Xu, Yanxing Suo, Qiao Cai, Yang Zhao

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

SAGERoute: Synergistic Analog Routing Considering Geometric and Electrical Constraints with Manual Design Compatibility.

Haoyi Zhang, Xiaohan Gao, Haoyang Luo, Jiahao Song, Xiyuan Tang, Junhua Liu, Yibo Lin, Runsheng Wang, Ru Huang

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

An 80.2-to-89.1dB-SNDR 24k-to-200kHz-BW VCO-Based Synthesized ?S ADC with 105dB SFDR in 28-nm CMOS.

Yi Zhong, Mingtao Zhan, Wei Wang, Xiyuan Tang, Lu Jie, Nan Sun

Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

A Calibration-Free 15-level/Cell eDRAM Computing-in-Memory Macro with 3T1C Current-Programmed Dynamic-Cascoded MLC achieving 233-to-304-TOPS/W 4b MAC.

Jiahao Song, Xiyuan Tang, Haoyang Luo, Haoyi Zhang, Xin Qiao, Zixuan Sun, Xiangxing Yang, Yuan Wang, Runsheng Wang, Ru Huang

Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

A 9.7fJ/Conv.-Step Capacitive Sensor Readout Circuit with Incremental Zoomed Time Domain Quantization.

Zilong Shen, Xiyuan Tang, Zhongyi Wu, Haoyang Luo, Zongnan Wang, Mingjie Liu, Xing Zhang, Yuan Wang

Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

2022

A 65 nm 73 kb SRAM-Based Computing-In-Memory Macro With Dynamic-Sparsity Controlling.

Xin Qiao, Jiahao Song, Xiyuan Tang, Haoyang Luo, Nanbing Pan, Xiaoxin Cui, Runsheng Wang, Yuan Wang

IEEE Trans. Circuits Syst. II Express Briefs, 2022

Low-Power SAR ADC Design: Overview and Survey of State-of-the-Art Techniques.

Xiyuan Tang, Jiaxin Liu, Yi Shen, Shaolan Li, Linxiao Shen, Arindam Sanyal, Kareem Ragab, Nan Sun

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

A 10-bit 100-MS/s SAR ADC With Always-On Reference Ripple Cancellation.

Yi Shen, Xiyuan Tang, Xin Xin, Shubin Liu, Zhangming Zhu, Nan Sun

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

A 0.004mm² 200MS/S Pipelined SAR ADC with kT/C Noise Cancellation and Robust Ring-Amp.

Mingtao Zhan, Lu Jie, Xiyuan Tang, Nan Sun

Proceedings of the IEEE International Solid-State Circuits Conference, 2022

A 0.014mm² 10kHz-BW Zoom-Incremental-Counting ADC Achieving 103dB SNDR and 100dB Full-Scale CMRR.

Lu Jie, Mingtao Zhan, Xiyuan Tang, Nan Sun

Proceedings of the IEEE International Solid-State Circuits Conference, 2022

A 0.37mm² 250kHz-BW 95dB-SNDR CTDSM with Low-Cost 2^nd-order Vector-Quantizer DEM.

Wei Shi, Xing Wang, Xiyuan Tang, Abhishek Mukherjee, Raviteja Theertham, Shanthi Pavan, Lu Jie, Nan Sun

Proceedings of the IEEE Custom Integrated Circuits Conference, 2022

Generative-Adversarial-Network-Guided Well-Aware Placement for Analog Circuits.

Keren Zhu, Hao Chen, Mingjie Liu, Xiyuan Tang, Wei Shi, Nan Sun, David Z. Pan

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

A Vector Pair Based DWA Algorithm for Linearity Enhancement of CDACs in the NS-SAR ADC.

Xiao Han, Xiyuan Tang, Yanxing Suo, Qiao Cai, Xinzi Xu, Tianwei Wan, Yang Zhao

Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

2021

TD-SRAM: Time-Domain-Based In-Memory Computing Macro for Binary Neural Networks.

Jiahao Song, Yuan Wang, Minguang Guo, Xiang Ji, Kaili Cheng, Yixuan Hu, Xiyuan Tang, Runsheng Wang, Ru Huang

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

A 13.8-ENOB Fully Dynamic Third-Order Noise-Shaping SAR ADC in a Single-Amplifier EF-CIFF Structure With Hardware-Reusing kT/C Noise Cancellation.

Tzu-Han Wang, Ruowei Wu, Vasu Gupta, Xiyuan Tang, Shaolan Li

IEEE J. Solid State Circuits, 2021

A 74.5-dB Dynamic Range 10-MHz BW CT-ΔΣ ADC With Distributed-Input VCO and Embedded Capacitive-π Network in 40-nm CMOS.

Abhishek Mukherjee, Miguel Gandara, Xiangxing Yang, Linxiao Shen, Xiyuan Tang, Chen-Kai Hsu, Nan Sun

IEEE J. Solid State Circuits, 2021

A 90-dB-SNDR Calibration-Free Fully Passive Noise-Shaping SAR ADC With 4× Passive Gain and Second-Order DAC Mismatch Error Shaping.

Jiaxin Liu, Xing Wang, Zijie Gao, Mingtao Zhan, Xiyuan Tang, Chen-Kai Hsu, Nan Sun

IEEE J. Solid State Circuits, 2021

A 77.1-dB-SNDR 6.25-MHz-BW Pipeline SAR ADC With Enhanced Interstage Gain Error Shaping and Quantization Noise Shaping.

Chen-Kai Hsu, Xiyuan Tang, Jiaxin Liu, Rui Xu, Wenda Zhao, Abhishek Mukherjee, Timothy R. Andeen, Nan Sun

IEEE J. Solid State Circuits, 2021

MAGICAL: An Open- Source Fully Automated Analog IC Layout System from Netlist to GDSII.

Hao Chen, Mingjie Liu, Biying Xu, Keren Zhu, Xiyuan Tang, Shaolan Li, Yibo Lin, Nan Sun, David Z. Pan

IEEE Des. Test, 2021

A 0.4-to-40MS/s 75.7dB-SNDR Fully Dynamic Event-Driven Pipelined ADC with 3-Stage Cascoded Floating Inverter Amplifier.

Xiyuan Tang, Xiangxing Yang, Jiaxin Liu, Wei Shi, David Z. Pan, Nan Sun

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

10.4 A 3.7mW 12.5MHz 81dB-SNDR 4th-Order CTDSM with Single-OTA and 2nd-Order NS-SAR.

Wei Shi, Jiaxin Liu, Abhishek Mukherjee, Xiangxing Yang, Xiyuan Tang, Linxiao Shen, Wenda Zhao, Nan Sun

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

27.1 A 250kHz-BW 93dB-SNDR 4^th-Order Noise-Shaping SAR Using Capacitor Stacking and Dynamic Buffering.

Jiaxin Liu, Dengquan Li, Yi Zhong, Xiyuan Tang, Nan Sun

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

OpenSAR: An Open Source Automated End-to-end SAR ADC Compiler.

Mingjie Liu, Xiyuan Tang, Keren Zhu, Hao Chen, Nan Sun, David Z. Pan

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Universal Symmetry Constraint Extraction for Analog and Mixed-Signal Circuits with Graph Neural Networks.

Hao Chen, Keren Zhu, Mingjie Liu, Xiyuan Tang, Nan Sun, David Z. Pan

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

An 81.5dB-DR 1.25MHz-BW VCO-Based CT ΔΣ ADC with Double-PFD Quantizer.

Yi Zhong, Xiyuan Tang, Jiaxin Liu, Wenda Zhao, Shaolan Li, Nan Sun

Proceedings of the IEEE Custom Integrated Circuits Conference, 2021

MAGICAL 1.0: An Open-Source Fully-Automated AMS Layout Synthesis Framework Verified With a 40-nm 1GS/s Δ∑ ADC.

Hao Chen, Mingjie Liu, Xiyuan Tang, Keren Zhu, Abhishek Mukherjee, Nan Sun, David Z. Pan

Proceedings of the IEEE Custom Integrated Circuits Conference, 2021

A 16Kb Transpose 6T SRAM In-Memory-Computing Macro based on Robust Charge-Domain Computing.

Jiahao Song, Yuan Wang, Xiyuan Tang, Runsheng Wang, Ru Huang

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021

2020

A Second-Order Purely VCO-Based CT ΔΣ ADC Using a Modified DPLL Structure in 40-nm CMOS.

Yi Zhong, Shaolan Li, Xiyuan Tang, Linxiao Shen, Wenda Zhao, Siliang Wu, Nan Sun

IEEE J. Solid State Circuits, 2020

A 0.025-mm² 0.8-V 78.5-dB SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL- ΔΣ M Structure.

Wenda Zhao, Shaolan Li, Biying Xu, Xiangxing Yang, Xiyuan Tang, Linxiao Shen, Nanshu Lu, David Z. Pan, Nan Sun

IEEE J. Solid State Circuits, 2020

A Fractional-<i>N</i> PLL With Space-Time Averaging for Quantization Noise Reduction.

Yanlong Zhang, Arindam Sanyal, Xueyi Yu, Xing Quan, Kailin Wen, Xiyuan Tang, Gang Jin, Li Geng, Nan Sun

IEEE J. Solid State Circuits, 2020

A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier.

Xiyuan Tang, Xiangxing Yang, Wenda Zhao, Chen-Kai Hsu, Jiaxin Liu, Linxiao Shen, Abhishek Mukherjee, Wei Shi, Shaolan Li, David Z. Pan, Nan Sun

IEEE J. Solid State Circuits, 2020

An Energy-Efficient Comparator With Dynamic Floating Inverter Amplifier.

Xiyuan Tang, Linxiao Shen, Begum Kasap, Xiangxing Yang, Wei Shi, Abhishek Mukherjee, David Z. Pan, Nan Sun

IEEE J. Solid State Circuits, 2020

An Energy-Efficient Time-Domain Incremental Zoom Capacitance-to-Digital Converter.

Xiyuan Tang, Shaolan Li, Xiangxing Yang, Linxiao Shen, Wenda Zhao, Randall P. Williams, Jiaxin Liu, Zhichao Tan, Neal A. Hall, David Z. Pan, Nan Sun

IEEE J. Solid State Circuits, 2020

A 10-bit 120-MS/s SAR ADC With Reference Ripple Cancellation Technique.

Yi Shen, Xiyuan Tang, Linxiao Shen, Wenda Zhao, Xin Xin, Shubin Liu, Zhangming Zhu, Visvesh Sathe, Nan Sun

IEEE J. Solid State Circuits, 2020

A 13-bit 0.005-mm² 40-MS/s SAR ADC With kT/C Noise Cancellation.

Jiaxin Liu, Xiyuan Tang, Wenda Zhao, Linxiao Shen, Nan Sun

IEEE J. Solid State Circuits, 2020

A 10-Bit 100-MS/s SAR ADC with Always-on Reference Ripple Cancellation.

Xiyuan Tang, Yi Shen, Xin Xin, Shubin Liu, Jueping Cai, Zhangming Zhu, Nan Sun

Proceedings of the IEEE Symposium on VLSI Circuits, 2020

A SAR ADC with Reduced kT/C Noise by Decoupling Noise PSD and BW.

Zhelu Li, Arnab Dutta, Abhishek Mukherjee, Xiyuan Tang, Linxiao Shen, Lenian He, Nan Sun

Proceedings of the IEEE Symposium on VLSI Circuits, 2020

9.5 A 13.5b-ENOB Second-Order Noise-Shaping SAR with PVT-Robust Closed-Loop Dynamic Amplifier.

Xiyuan Tang, Xiangxing Yang, Wenda Zhao, Chen-Kai Hsu, Jiaxin Liu, Linxiao Shen, Abhishek Mukherjee, Wei Shi, David Z. Pan, Nan Sun

Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

9.3 A 40kHz-BW 90dB-SNDR Noise-Shaping SAR with 4× Passive Gain and 2^nd-Order Mismatch Error Shaping.

Jiaxin Liu, Xing Wang, Zijie Gao, Mingtao Zhan, Xiyuan Tang, Nan Sun

Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

16.5 A 13b 0.005mm² 40MS/s SAR ADC with kT/C Noise Cancellation.

Jiaxin Liu, Xiyuan Tang, Wenda Zhao, Linxiao Shen, Nan Sun

Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

An Energy-Efficient Flexible Capacitive Pressure Sensing System.

Yuxuan Huang, Qinghang Zhao, Xiyuan Tang, Fang Su, Nan Sun, Huazhong Yang, Yongpan Liu

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Toward Silicon-Proven Detailed Routing for Analog and Mixed-Signal Circuits.

Hao Chen, Keren Zhu, Mingjie Liu, Xiyuan Tang, Nan Sun, David Z. Pan

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Effective Analog/Mixed-Signal Circuit Placement Considering System Signal Flow.

Keren Zhu, Hao Chen, Mingjie Liu, Xiyuan Tang, Nan Sun, David Z. Pan

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Towards Decrypting the Art of Analog Layout: Placement Quality Prediction via Transfer Learning.

Mingjie Liu, Keren Zhu, Jiaqi Gu, Linxiao Shen, Xiyuan Tang, Nan Sun, David Z. Pan

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Closing the Design Loop: Bayesian Optimization Assisted Hierarchical Analog Layout Synthesis.

Mingjie Liu, Keren Zhu, Xiyuan Tang, Biying Xu, Wei Shi, Nan Sun, David Z. Pan

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

A 77.1-dB 6.25-MHz-BW Pipeline SAR ADC with Enhanced Interstage Gain Error Shaping and Quantization Error Shaping.

Chen-Kai Hsu, Xiyuan Tang, Wenda Zhao, Rui Xu, Abhishek Mukherjee, Timothy R. Andeen, Nan Sun

Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020

A Power-Efficient 13-Tap FIR filter and an IIR Filter Embedded in a 10-bit SAR ADC.

Xin Xin, Linxiao Shen, Xiyuan Tang, Yi Shen, Jueping Cai, Nan Sun

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2020

S³DET: Detecting System Symmetry Constraints for Analog Circuits with Graph Similarity.

Mingjie Liu, Wuxi Li, Keren Zhu, Biying Xu, Yibo Lin, Linxiao Shen, Xiyuan Tang, Nan Sun, David Z. Pan

Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019

A 10-b 600-MS/s 2-Way Time-Interleaved SAR ADC With Mean Absolute Deviation-Based Background Timing-Skew Calibration.

Jeonggoo Song, Kareem Ragab, Xiyuan Tang, Nan Sun

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Error-Feedback Mismatch Error Shaping for High-Resolution Data Converters.

Jiaxin Liu, Chen-Kai Hsu, Xiyuan Tang, Shaolan Li, Guangjun Wen, Nan Sun

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A Two-Step ADC With a Continuous-Time SAR-Based First Stage.

Linxiao Shen, Nan Sun, Yi Shen, Zhelu Li, Wei Shi, Xiyuan Tang, Shaolan Li, Wenda Zhao, Mantian Zhang, Zhangming Zhu

IEEE J. Solid State Circuits, 2019

Advances in Voltage-Controlled-Oscillator-Based ΔΣ ADCs.

Shaolan Li, Arindam Sanyal, Kyoungtae Lee, Yeonam Yoon, Xiyuan Tang, Yi Zhong, Kareem Ragab, Nan Sun

IEICE Trans. Electron., 2019

An Energy-Efficient Comparator with Dynamic Floating Inverter Pre-Amplifier.

Xiyuan Tang, Begum Kasap, Linxiao Shen, Xiangxing Yang, Wei Shi, Nan Sun

Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A 0.6-V Tail-Less Inverter Stacking Amplifier with 0.96 PEF.

Linxiao Shen, Abhishek Mukherjee, Shaolan Li, Xiyuan Tang, Nanshu Lu, Nan Sun

Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A 16fJ/Conversion-Step Time-Domain Two-Step Capacitance-to-Digital Converter.

Xiyuan Tang, Shaolan Li, Linxiao Shen, Wenda Zhao, Xiangxing Yang, Randy Williams, Jiaxin Liu, Zhichao Tan, Neal A. Hall, Nan Sun

Proceedings of the IEEE International Solid- State Circuits Conference, 2019

A 0.01mm² 25µW 2MS/s 74dB-SNDR Continuous-Time Pipelined-SAR ADC with 120fF Input Capacitor.

Linxiao Shen, Yi Shen, Xiyuan Tang, Chen-Kai Hsu, Wei Shi, Shaolan Li, Wenda Zhao, Abhishek Mukherjee, Nan Sun

Proceedings of the IEEE International Solid- State Circuits Conference, 2019

GeniusRoute: A New Analog Routing Paradigm Using Generative Neural Network Guidance.

Keren Zhu, Mingjie Liu, Yibo Lin, Biying Xu, Shaolan Li, Xiyuan Tang, Nan Sun, David Z. Pan

Proceedings of the International Conference on Computer-Aided Design, 2019

MAGICAL: Toward Fully Automated Analog IC Layout Leveraging Human and Machine Intelligence: Invited Paper.

Biying Xu, Keren Zhu, Mingjie Liu, Yibo Lin, Shaolan Li, Xiyuan Tang, Nan Sun, David Z. Pan

Proceedings of the International Conference on Computer-Aided Design, 2019

WellGAN: Generative-Adversarial-Network-Guided Well Generation for Analog/Mixed-Signal Circuit Layout.

Biying Xu, Yibo Lin, Xiyuan Tang, Shaolan Li, Linxiao Shen, Nan Sun, David Z. Pan

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

A 2.4-GHz ΔΣ Fractional-N Synthesizer with Space-Time Averaging for Noise Reduction.

Yanlong Zhang, Arindam Sanyal, Xing Quan, Kailin Wen, Xiyuan Tang, Gang Jin, Li Geng, Nan Sun

Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

A 10b 120MS/s SAR ADC with Reference Ripple Cancellation Technique.

Xiyuan Tang, Yi Shen, Linxiao Shen, Wenda Zhao, Zhangming Zhu, Visvesh Sathe, Nan Sun

Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

A 0.025-mm² 0.8-V 78.5dB-SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL-ΔΣM Structure.

Shaolan Li, Wenda Zhao, Biying Xu, Xiangxing Yang, Xiyuan Tang, Linxiao Shen, Nanshu Lu, David Z. Pan, Nan Sun

Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

S²-PM: semi-supervised learning for efficient performance modeling of analog and mixed signal circuits.

Mohamed Baker Alawieh, Xiyuan Tang, David Z. Pan

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018

A Second-Order Purely VCO-Based CT Δ∑ ADC Using a Modified DPLL in 40-nm CMOS.

Yi Zhong, Shaolan Li, Arindam Sanyal, Xiyuan Tang, Linxiao Shen, Siliang Wu, Nan Sun

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2017

A 0.95-mW 6-b 700-MS/s Single-Channel Loop-Unrolled SAR ADC in 40-nm CMOS.

Long Chen, Kareem Ragab, Xiyuan Tang, Jeonggoo Song, Arindam Sanyal, Nan Sun

IEEE Trans. Circuits Syst. II Express Briefs, 2017

A 10-b 800-MS/s Time-Interleaved SAR ADC With Fast Variance-Based Timing-Skew Calibration.

Jeonggoo Song, Kareem Ragab, Xiyuan Tang, Nan Sun

IEEE J. Solid State Circuits, 2017

A 0.7-V 0.6-µW 100-kS/s Low-Power SAR ADC With Statistical Estimation-Based Noise Reduction.

Long Chen, Xiyuan Tang, Arindam Sanyal, Yeonam Yoon, Jie Cong, Nan Sun

IEEE J. Solid State Circuits, 2017

A 10-b 2b/cycle 300MS/s SAR ADC with a single differential DAC in 40nm CMOS.

Jeonggoo Song, Xiyuan Tang, Nan Sun

Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

A pipelined SAR ADC reusing the comparator as residue amplifier.

Miguel Gandara, Wenjuan Guo, Xiyuan Tang, Long Chen, Yeonam Yoon, Nan Sun

Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

A 1.5fJ/conv-step 10b 100kS/s SAR ADC with gain-boosted dynamic comparator.

Xiyuan Tang, Long Chen, Jeonggoo Song, Nan Sun

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

2016

Comparator common-mode variation effects analysis and its application in SAR ADCs.

Long Chen, Arindam Sanyal, Ji Ma, Xiyuan Tang, Nan Sun

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A 10-b 750µW 200MS/s fully dynamic single-channel SAR ADC in 40nm CMOS.

Xiyuan Tang, Long Chen, Jeonggoo Song, Nan Sun

Proceedings of the ESSCIRC Conference 2016: 42^nd European Solid-State Circuits Conference, 2016

A 10-b 800MS/s time-interleaved SAR ADC with fast timing-skew calibration.

Jeonggoo Song, Kareem Ragab, Xiyuan Tang, Nan Sun

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015

A 0.04-mm² 0.9-mW 71-dB SNDR distributed modular AS ADC with VCO-based integrator and digital DAC calibration.

Yeonam Yoon, Kyoungtae Lee, Sungjin Hong, Xiyuan Tang, Long Chen, Nan Sun

Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

A 10.5-b ENOB 645 nW 100kS/s SAR ADC with statistical estimation based noise reduction.

Long Chen, Xiyuan Tang, Arindam Sanyal, Yeonam Yoon, Jie Cong, Nan Sun

Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015