Xiumin Xu

According to our database1, Xiumin Xu authored at least 9 papers between 2017 and 2018.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

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Bibliography

2018
A High Reliability FPGA Chip Identification Generator Based on PDLs.
Proceedings of the 27th IEEE Asian Test Symposium, 2018

An All-Digital and Jitter-Quantizing True Random Number Generator in SRAM-Based FPGAs.
Proceedings of the 27th IEEE Asian Test Symposium, 2018

A Low-Cost High-Efficiency True Random Number Generator on FPGAs.
Proceedings of the 27th IEEE Asian Test Symposium, 2018

2017
Double-Node-Upset-Resilient Latch Design for Nanoscale CMOS Technology.
IEEE Trans. Very Large Scale Integr. Syst., 2017

A Region-Based Through-Silicon via Repair Method for Clustered Faults.
IEICE Trans. Electron., 2017

Highly Robust Double Node Upset Resilient Hardened Latch Design.
IEICE Trans. Electron., 2017

A highly reliable butterfly PUF in SRAM-based FPGAs.
IEICE Electron. Express, 2017

A single event transient detector in SRAM-based FPGAs.
IEICE Electron. Express, 2017

Vernier ring based pre-bond through silicon vias test in 3D ICs.
IEICE Electron. Express, 2017


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