Xiulong Wu

According to our database, Xiulong Wu authored at least 74 papers between 2006 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2025

An RISC-V PPA-Fusion Cooperative Optimization Framework Based on Hybrid Strategies.

Tianning Gao, Yifan Wang, Ming Zhu, Xiulong Wu, Dian Zhou, Zhaori Bi

IEEE Trans. Very Large Scale Integr. Syst., January, 2025

A Temperature-Compensated Ku-Band Four-Beam Phased-Array Receiver With Low Attenuation and Relative Phase Variations.

Shichao Jin, Jiaxing Sun, Zhuoheng Xie, Bo Huang, Dunge Liu, Yu-Qian Yang, Chenyu Mei, Jun Huang, Chenyu Wang, Xiulong Wu, Yujian Cheng

IEEE Trans. Circuits Syst. II Express Briefs, January, 2025

Hybrid MOSFET-TFET 11T SRAM cell with high write speed and free half-selected disturbance.

Wenjuan Lu, Chuang Wang, Wei Hu, Chenghu Dai, Chunyu Peng, Zhiting Lin, Xiulong Wu

Microelectron. J., 2025

2024

High-Performance Latch Designs of Double-Node-Upset Self-Recovery and Triple-Node-Upset Tolerance for Aerospace Applications.

Chunyu Peng, Lang Tian, Licai Hao, Qiang Zhao, Chenghu Dai, Zhiting Lin, Xiulong Wu

IEEE Trans. Aerosp. Electron. Syst., October, 2024

Timing Optimization Model and PVT Tracked Scheme for STT-MRAM Voltage-Mode Sense.

Yongliang Zhou, Xiao Lin, Zixuan Zhou, Yingxue Sun, Yiming Wei, Zhen Yang, Chengxing Dai, JingXue Zhong, Xiulong Wu, Chunyu Peng

IEEE Trans. Circuits Syst. I Regul. Pap., September, 2024

A Computing In-Memory Multibit Multiplication Based on Decoupling and In-Array Storing.

Jin Zhang, Zhongzhen Tong, Hao Wang, Xin Wang, Qiang Zhao, Jian Zhou, Jiaqun Wang, Zhiting Lin, Xiulong Wu

IEEE Trans. Circuits Syst. I Regul. Pap., August, 2024

A 2.77-dB NF K-Band Four-Element Dual-Beam Phased-Array Receiver With 39-dB Tx-Band Rejection for SATCOM Applications.

Jiaxing Sun, Shichao Jin, Zhuoheng Xie, Yu-Qian Yang, Bo Huang, Dunge Liu, Chenyu Mei, Jinhuai Su, Jun Huang, Xiulong Wu

IEEE Trans. Circuits Syst. II Express Briefs, June, 2024

Low-Cost and Highly Robust Quadruple Node Upset Tolerant Latch Design.

Licai Hao, Yaling Wang, Yunlong Liu, Shiyu Zhao, Xinyi Zhang, Yang Li, Wenjuan Lu, Chunyu Peng, Qiang Zhao, Yongliang Zhou, Chenghu Dai, Zhiting Lin, Xiulong Wu

IEEE Trans. Very Large Scale Integr. Syst., May, 2024

Soft-Error-Immune Quadruple-Node-Upset Tolerant Latch Based on Polarity Design and Source-Isolation Technologies.

Licai Hao, Xinyi Zhang, Chenghu Dai, Qiang Zhao, Wenjuan Lu, Chunyu Peng, Yongliang Zhou, Zhiting Lin, Xiulong Wu

IEEE Trans. Very Large Scale Integr. Syst., April, 2024

Flip Point Offset-Compensation Sense Amplifier With Sensing-Margin-Enhancement for Dynamic Random-Access Memory.

Li Liu, Dele Tai, Bin Qiang, Lijun Guan, Chunyu Peng, Chenghu Dai, Licai Hao, Wenjuan Lu, Zhiting Lin, Qiang Zhao, Xiulong Wu

IEEE Trans. Circuits Syst. II Express Briefs, April, 2024

A High Throughput In-MRAM-Computing Scheme Using Hybrid p-SOT-MTJ/GAA-CNTFET.

Zhongzhen Tong, Yilin Xu, Yunlong Liu, Xinrui Duan, Hao Tang, Suteng Zhao, Chenghang Li, Zhiting Lin, Xiulong Wu, Zhaohao Wang, Xiaoyang Lin

IEEE Trans. Circuits Syst. I Regul. Pap., February, 2024

A 9T-SRAM in-memory computing macro for Boolean logic and multiply-and-accumulate operations.

Chenghu Dai, Zihua Ren, Lijun Guan, Haitao Liu, Mengya Gao, Wenjuan Lu, Zhiyong Pang, Chunyu Peng, Xiulong Wu

Microelectron. J., February, 2024

A CFMB STT-MRAM-Based Computing-in-Memory Proposal With Cascade Computing Unit for Edge AI Devices.

Yongliang Zhou, Zixuan Zhou, Yiming Wei, Zhen Yang, Xiao Lin, Chenghu Dai, Licai Hao, Chunyu Peng, Hao Cai, Xiulong Wu

IEEE Trans. Circuits Syst. I Regul. Pap., January, 2024

An 8b-Precison 16-Kb FDSOI 8T SRAM CIM macro based on time-domain for energy-efficient edge AI devices.

Yongliang Zhou, Yiming Wei, Tianzhu Xiong, Zixuan Zhou, Zhen Yang, Xiao Lin, Wei Hu, Xiulong Wu, Chunyu Peng

Microelectron. J., 2024

Design of polarity hardening SRAM for mitigating single event multiple node upsets.

Shiyu Zhao, Qiang Zhao, Licai Hao, Chunyu Peng, Yaling Wang, Wenjuan Lu, Zhiting Lin, Xiulong Wu

Microelectron. J., 2024

An 11-bit two-step column-shared ADC based on Flash/SS architecture for CMOS image sensor.

Qiang Zhao, Jitao Xu, Chunhui Fan, Ziming Wang, Ruitong Hu, Xin Li, Zhigang Li, Licai Hao, Chunyu Peng, Zhiting Lin, Xiulong Wu

Microelectron. J., 2024

Configurable in-memory computing architecture based on dual-port SRAM.

Yue Zhao, Yunlong Liu, Jian Zheng, Zhongzhen Tong, Xin Wang, Runru Yu, Xiulong Wu, Yongliang Zhou, Chunyu Peng, Wenjuan Lu, Qiang Zhao, Zhiting Lin

Microelectron. J., 2024

High energy efficient and configurable CIM macro for image processing.

Chunyu Peng, Shengyuan Yan, Huayi Ding, Yana Wang, Wenjuan Lu, Chenghu Dai, Xin Li, Wei Hu, Xiulong Wu

Microelectron. J., 2024

Cross-coupled 4T2R multi-logic in-memory computing circuit design.

Zhiting Lin, Changxin Yue, Ke Li, Qiushi Feng, Siyan Li, Yue Zhao, Yuanyang Wang, Jiaqi Chen, Wenjuan Lu, Chunyu Peng, Qiang Zhao, Chenghu Dai, Licai Hao, Xiulong Wu

Microelectron. J., 2024

A 28-nm 9T SRAM-based CIM macro with capacitance weighting module and redundant array-assisted ADC.

Zhiting Lin, Runru Yu, Da Huo, Qingchuan Zhu, Miao Long, Yongqi Qin, Yanchun Liu, Lintao Chen, Simin Wang, Ting Wang, Yousheng Xing, Zeshi Wen, Yu Liu, Xin Li, Chenghu Dai, Qiang Zhao, Chunyu Peng, Xiulong Wu

Microelectron. J., 2024

Corrigendum to "A 9T-SRAM based computing-in-memory with redundant unit and digital operation for boolean logic and MAC" [145, March 2024, 106124.

Xin Li, Mengya Gao, Zihua Ren, Kefeng Yu, Wenjuan Lu, Chenghu Dai, Wei Hu, Chunyu Peng, Xiulong Wu

Microelectron. J., 2024

A 9T-SRAM based computing-in-memory with redundant unit and digital operation for boolean logic and MAC.

Xin Li, Mengya Gao, Zihua Ren, Kefeng Yu, Wenjuan Lu, Chenghu Dai, Wei Hu, Chunyu Peng, Xiulong Wu

Microelectron. J., 2024

A Timing-Shared Adaptive Sensing Methodology for Low-Voltage SRAM.

Yongliang Zhou, Zhen Yang, Yiming Wei, Xiao Lin, Saiai Wu, Wenjuan Lu, Chunyu Peng, Xin Li, Xiulong Wu

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

SRAM-Based Digital CIM Macro for Linear Interpolation and MAC.

Zhiting Lin, Yunlong Liu, Yaling Wang, Yue Zhao, Chunyu Peng, Xiulong Wu

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2023

Novel radiation-hardened-by-design (RHBD) 14T memory cell for aerospace applications in 65 nm CMOS technology.

Pengfei Li, Xiuying Wang, Yin Zhang, Haoyu Wang, Jianjie Lu, Qiang Zhao, Licai Hao, Chunyu Peng, Wenjuan Lu, Zhiting Lin, Xiulong Wu

Microelectron. J., November, 2023

In-Memory Transposable Multibit Multiplication Based on Diagonal Symmetry Weight Block.

Zhongzhen Tong, Yue Zhao, Jin Zhang, Zhiting Lin, Xiaoyang Lin, Xiulong Wu

IEEE Trans. Very Large Scale Integr. Syst., September, 2023

A Fully Digital SRAM-Based Four-Layer In-Memory Computing Unit Achieving Multiplication Operations and Results Store.

Zhiting Lin, Shaoying Zhang, Qian Jin, Jianping Xia, Yunwei Liu, Kefeng Yu, Jian Zheng, Xiaoming Xu, Xing Fan, Ke Li, Zhongzhen Tong, Xiulong Wu, Wenjuan Lu, Chunyu Peng, Qiang Zhao

IEEE Trans. Very Large Scale Integr. Syst., June, 2023

In Situ Storing 8T SRAM-CIM Macro for Full-Array Boolean Logic and Copy Operations.

Zhiting Lin, Zhongzhen Tong, Fangming Wang, Jin Zhang, Yue Zhao, Peng Sun, Tian Xu, Cheng Zhang, Xingwei Li, Xiulong Wu, Wenjuan Lu, Chunyu Peng, Qiang Zhao, Junning Chen

IEEE J. Solid State Circuits, May, 2023

High Restore Yield NVSRAM Structures With Dual Complementary RRAM Devices for High-Speed Applications.

Zhiting Lin, Min Chen, Peng Sun, Xiulong Wu, Qiang Zhao, Wenjuan Lu, Chunyu Peng

IEEE Trans. Very Large Scale Integr. Syst., April, 2023

Threshold Switching Memristor-Based Voltage Regulative Circuit.

Zuheng Wu, Changwei Zhang, Jianxun Zou, Chunyu Peng, Xiulong Wu

IEEE Trans. Circuits Syst. II Express Briefs, March, 2023

Design of radiation-hardened memory cell by polar design for space applications.

Licai Hao, Li Liu, Qi Shi, Bin Qiang, Zhengya Li, Nianlong Liu, Chenghu Dai, Qiang Zhao, Chunyu Peng, Wenjuan Lu, Zhiting Lin, Xiulong Wu

Microelectron. J., February, 2023

Bit-line leakage current tracking and self-compensation circuit for SRAM reliability design.

Chenghu Dai, Yuanyuan Du, Qi Shi, Ruixuan Wang, Hao Zheng, Wenjuan Lu, Chunyu Peng, Licai Hao, Zhiting Lin, Xiulong Wu

Microelectron. J., February, 2023

Write-enhanced and radiation-hardened SRAM for multi-node upset tolerance in space-radiation environments.

Qiang Zhao, Hanwen Dong, Chunyu Peng, Wenjuan Lu, Zhiting Lin, Junning Chen, Xiulong Wu

Int. J. Circuit Theory Appl., January, 2023

Radiation-hardened 14T SRAM cell by polar design for space applications.

Licai Hao, Bin Qiang, Chenghu Dai, Chunyu Peng, Wenjuan Lu, Zhiting Lin, Li Liu, Qiang Zhao, Xiulong Wu, Fei Sun

IEICE Electron. Express, 2023

First Foundry Platform Demonstration of Hybrid Tunnel FET and MOSFET Circuits Based on a Novel Laminated Well Isolation Technology.

Kaifeng Wang, Yongqin Wu, Ye Ren, Renjie Wei, Zerui Chen, Jianfeng Hang, Zhixuan Wang, Fangxing Zhang, Lining Zhang, Chunyu Peng, Xiulong Wu, Le Ye, Kai Zheng, Jin Kang, Xusheng Wu, Weihai Bu, Ru Huang, Qianqian Huang

Proceedings of the 53rd IEEE European Solid-State Device Research Conference, 2023

2022

Configurable Memory With a Multilevel Shared Structure Enabling In-Memory Computing.

Yue Zhao, Zhiting Lin, Xiulong Wu, Qiang Zhao, Wenjuan Lu, Chunyu Peng, Zhongzhen Tong, Junning Chen

IEEE Trans. Very Large Scale Integr. Syst., 2022

In-Memory Multibit Multiplication Based on Bitline Shifting.

Jin Zhang, Zhiting Lin, Xiulong Wu, Zhongzhen Tong, Chunyu Peng, Wenjuan Lu, Qiang Zhao, Hongbiao Wu, Junning Chen

IEEE Trans. Circuits Syst. II Express Briefs, 2022

Offset-Compensation High-Performance Sense Amplifier for Low-Voltage DRAM Based on Current Mirror and Switching Point.

Pei Huang, Kuan-Chang Chang, Junlin Ge, Chunyu Peng, Xiulong Wu, Junning Chen, Zhiting Lin

IEEE Trans. Circuits Syst. II Express Briefs, 2022

An offset cancellation technique for SRAM sense amplifier based on relation of the delay and offset.

Yue Zhao, Jinkai Wang, Zhongzhen Tong, Xiulong Wu, Chunyu Peng, Wenjuan Lu, Qiang Zhao, Zhiting Lin

Microelectron. J., 2022

Novel radiation-hardened latch design for space-radiation environments.

Qiang Zhao, Hanwen Dong, Licai Hao, Xiuying Wang, Chunyu Peng, Xiulong Wu

IEICE Electron. Express, 2022

Spike-Enabled Audio Learning in Multilevel Synaptic Memristor Array-Based Spiking Neural Network.

Xulei Wu, Bingjie Dang, Hong Wang, Xiulong Wu, Yuchao Yang

Adv. Intell. Syst., 2022

2021

Reverse Bias Current Eliminated, Read-Separated, and Write-Enhanced Tunnel FET SRAM.

Chunyu Peng, Zhou Yang, Zhiting Lin, Xiulong Wu, Xuan Li

IEEE Trans. Circuits Syst. II Express Briefs, 2021

Half-Select Disturb-Free 10T Tunnel FET SRAM Cell With Improved Noise Margin and Low Power Consumption.

Zhiting Lin, Luanyun Li, Xiulong Wu, Chunyu Peng, Wenjuan Lu, Qiang Zhao

IEEE Trans. Circuits Syst. II Express Briefs, 2021

Two-Direction In-Memory Computing Based on 10T SRAM With Horizontal and Vertical Decoupled Read Ports.

Zhiting Lin, Zhiyong Zhu, Honglan Zhan, Chunyu Peng, Xiulong Wu, Yuan Yao, Jianchao Niu, Junning Chen

IEEE J. Solid State Circuits, 2021

Cascade Current Mirror to Improve Linearity and Consistency in SRAM In-Memory Computing.

Zhiting Lin, Honglan Zhan, Zhongwei Chen, Chunyu Peng, Xiulong Wu, Wenjuan Lu, Qiang Zhao, Xuan Li, Junning Chen

IEEE J. Solid State Circuits, 2021

2020

Novel Write-Enhanced and Highly Reliable RHPD-12T SRAM Cells for Space Applications.

Qiang Zhao, Chunyu Peng, Junning Chen, Zhiting Lin, Xiulong Wu

IEEE Trans. Very Large Scale Integr. Syst., 2020

In-Memory Computing With Double Word Lines and Three Read Ports for Four Operands.

Zhiting Lin, Honglan Zhan, Xuan Li, Chunyu Peng, Wenjuan Lu, Xiulong Wu, Junning Chen

IEEE Trans. Very Large Scale Integr. Syst., 2020

Multiple Sharing 7T1R Nonvolatile SRAM With an Improved Read/Write Margin and Reliable Restore Yield.

Zhiting Lin, Yong Wang, Chunyu Peng, Xiulong Wu, Xuan Li, Junning Chen

IEEE Trans. Very Large Scale Integr. Syst., 2020

A Self-Matching Complementary-Reference Sensing Scheme for High-Speed and Reliable Toggle Spin Torque MRAM.

Jinkai Wang, Chenyu Lian, Yining Bai, Guanda Wang, Zhizhong Zhang, Zhenyi Zheng, Lei Chen, Kelian Lin, Kun Zhang, Youguang Zhang, Xiulong Wu, Sorin Cotofana, Yue Zhang

IEEE Trans. Circuits Syst., 2020

Challenges and Solutions of the TFET Circuit Design.

Zhiting Lin, Panpan Chen, Le Ye, Xu Yan, Lanzhi Dong, Shuguang Zhang, Zhou Yang, Chunyu Peng, Xiulong Wu, Junning Chen

IEEE Trans. Circuits Syst., 2020

A new reading mode based on balanced pre-charging and group decoding.

Wenjuan Lu, Guoying Qin, Zhiting Lin, Xiulong Wu, Chunyu Peng

IEICE Electron. Express, 2020

14.2 A 65nm 24.7µJ/Frame 12.3mW Activation-Similarity-Aware Convolutional Neural Network Video Processor Using Hybrid Precision, Inter-Frame Data Reuse and Mixed-Bit-Width Difference-Frame Data Codec.

Zhe Yuan, Yixiong Yang, Jinshan Yue, Ruoyang Liu, Xiaoyu Feng, Zhiting Lin, Xiulong Wu, Xueqing Li, Huazhong Yang, Yongpan Liu

Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

An Efficient and Robust Yield Optimization Method for High-dimensional SRAM Circuits.

Xiaodong Wang, Tianchen Gu, Changhao Yan, Xiulong Wu, Fan Yang, Sheng-Guo Wang, Dian Zhou, Xuan Zeng

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019

Radiation-Hardened 14T SRAM Bitcell With Speed and Power Optimized for Space Application.

Chunyu Peng, Jiati Huang, Changyong Liu, Qiang Zhao, Songsong Xiao, Xiulong Wu, Zhiting Lin, Junning Chen, Xuan Zeng

IEEE Trans. Very Large Scale Integr. Syst., 2019

Architectural Exploration to Address the Reliability Challenges for ReRAM-Based Buffer in SSD.

Xiaoqing Zhao, Hongbin Sun, Longjun Liu, Yang Yang, Liangliang Dai, Xiulong Wu, Ruizhi Zhang, Jianxiao Wang, Nanning Zheng

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Physical mechanism study of N-well doping effects on the single-event transient characteristic of PMOS.

Qiang Zhao, Chunyu Peng, Changyong Liu, Xiulong Wu

IEICE Electron. Express, 2019

An inverter chain with parallel output nodes for eliminating single-event transient pulse.

Changyong Liu, Zhiting Lin, Xiulong Wu, Chunyu Peng, Qiang Zhao, Xuan Li, Junning Chen, Xuan Zeng, Xiangdong Hu

IEICE Electron. Express, 2019

A single event upset tolerant latch with parallel nodes.

Changyong Liu, Nianlong Liu, Zhiting Lin, Xiulong Wu, Chunyu Peng, Qiang Zhao, Xuan Li, Junning Chen, Xuan Zeng, Xiangdong Hu

IEICE Electron. Express, 2019

High speed and reliable Sensing Scheme with Three Voltages for STT-MRAM.

Jinkai Wang, Yue Zhang, Chenyu Lian, Guanda Wang, Kun Zhang, Xiulong Wu, Youguang Zhang, Weisheng Zhao

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2019

2018

Average 7T1R Nonvolatile SRAM With R/W Margin Enhanced for Low-Power Application.

Chunyu Peng, Songsong Xiao, Wenjuan Lu, Jingbo Zhang, Xiulong Wu, Junning Chen, Zhiting Lin

IEEE Trans. Very Large Scale Integr. Syst., 2018

Offset voltage suppressed sense amplifier with self-adaptive distribution transformation technique.

Chunyu Peng, Lingyu Kong, Xiulong Wu, Zhiting Lin, Hua Xu, Junning Chen, Xuan Zeng

IEICE Electron. Express, 2018

A dual-output hardening design of inverter chain for P-hit single-event transient pulse elimination.

Changyong Liu, Chunyu Peng, Zhiting Lin, Xiulong Wu, Ziyang Chen, Qiang Zhao, Xuan Li, Junning Chen, Xuan Zeng, Xiangdong Hu

IEICE Electron. Express, 2018

Picowatt 0.5 V supply with 3 ppm/°C CMOS voltage reference for energy harvesting system.

Jingfeng Liu, Quan Li, Xin Liu, Zhiqiang Li, Yu Liu, Zhiting Lin, Xiulong Wu

IEICE Electron. Express, 2018

2017

A Pipeline Replica Bitline Technique for Suppressing Timing Variation of SRAM Sense Amplifiers in a 28-nm CMOS Process.

Zhiting Lin, Xiulong Wu, Zhi Li, Lijun Guan, Chunyu Peng, Changyong Liu, Junning Chen

IEEE J. Solid State Circuits, 2017

A radiation harden enhanced Quatro (RHEQ) SRAM cell.

Chunyu Peng, Ziyang Chen, Jingbo Zhang, Songsong Xiao, Changyong Liu, Xiulong Wu, Zhiting Lin

IEICE Electron. Express, 2017

2016

Read/write margin enhanced 10T SRAM for low voltage application.

Chunyu Peng, Lijun Guan, Wenjuan Lu, Xiulong Wu, Xincun Ji

IEICE Electron. Express, 2016

Additive-calibration scheme for leakage compensation of low voltage SRAM.

Chunyu Peng, Xiangwen An, Zhiting Lin, Xiulong Wu, Wei Hong

IEICE Electron. Express, 2016

A yield-enhanced global optimization methodology for analog circuit based on extreme value theory.

Minghua Li, Guanming Huang, Xiulong Wu, Liuxi Qian, Xuan Zeng, Dian Zhou

Sci. China Inf. Sci., 2016

2015

Analyzing and modeling mobility for infrastructure-less communication.

Zhiting Lin, Xiulong Wu

J. Netw. Comput. Appl., 2015

Human dynamics in mobile social networks: A study of inter-node relationships.

Zhiting Lin, Chunyu Peng, Xiulong Wu, Xiufang Jiang

Proceedings of the 12th International Conference on Fuzzy Systems and Knowledge Discovery, 2015

2013

The Design of High Performance, Low Power Triple-Track Magnetic Sensor Chip.

Xiulong Wu, Minghua Li, Zhiting Lin, Mengyuan Xi, Junning Chen

Sensors, 2013

2012

Bitline Leakage Current Compensation Circuit for High-Performance SRAM Design.

Ruixing Lu, Na Bai, Baitao Lv, Jiafeng Zhu, Xiulong Wu

Proceedings of the Seventh IEEE International Conference on Networking, 2012

2011

A 12T Subthreshold SRAM Bit-Cell for Medical Device Application.

Chen Hu, Jun Yang, Meng Zhang, Xiulong Wu

Proceedings of the 2011 International Conference on Cyber-Enabled Distributed Computing and Knowledge Discovery, 2011

2006

A Compact Equivalent Circuit Model of HVLDMOS and Application in HIVC Design.

Shan Gao, Junning Chen, Daoming Ke, Xiulong Wu

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006