Xinmiao Zhang

IEEE Trans. Circuits Syst. I Regul. Pap., November, 2024

Low-Complexity Parallel Chien Search Architecture Based on Vandermonde Matrix Decomposition.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., September, 2024

Modified Extended Integrated Interleaved Codes.

[BibT_eX]

[DOI]

IEEE Commun. Lett., May, 2024

Hardware Circuits and Systems Design for Post-Quantum Cryptography - A Tutorial Brief.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, March, 2024

Low-Complexity Ciphertext Multiplication for CKKS Homomorphic Encryption.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, March, 2024

Generalized Integrated Interleaved Codes for High-Density DRAMs.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, January, 2024

Three-Input Ciphertext Multiplication for Homomorphic Encryption.

[BibT_eX]

[DOI]

CoRR, 2024

Efficient Homomorphically Encrypted Convolutional Neural Network Without Rotation.

[BibT_eX]

[DOI]

CoRR, 2024

Highly Efficient Parallel Row-Layered Min-Sum MDPC Decoder for McEliece Cryptosystem.

[BibT_eX]

[DOI]

CoRR, 2024

Low-Latency Parallel Row-Layered Min-sum MDPC Decoder for McEliece Cryptosystem.

[BibT_eX]

[DOI]

Proceedings of the IEEE Workshop on Signal Processing Systemsm, 2024

Low-Complexity Integer Divider Architecture for Homomorphic Encryption.

[BibT_eX]

[DOI]

Proceedings of the IEEE Workshop on Signal Processing Systemsm, 2024

Improved Ciphertext Multiplication for RNS-CKKS Homomorphic Encryption.

[BibT_eX]

[DOI]

Proceedings of the IEEE Workshop on Signal Processing Systemsm, 2024

2023

Low-Complexity Parallel Min-Sum Medium-Density Parity-Check Decoder for McEliece Cryptosystem.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023

Joint Protection Scheme for Deep Neural Network Hardware Accelerators and Models.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023

Sparsity-Aware Medium-Density Parity-Check Decoder for McEliece Cryptosystems.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, September, 2023

High-Speed VLSI Architectures for Modular Polynomial Multiplication via Fast Filtering and Applications to Lattice-Based Cryptography.

[BibT_eX]

[DOI]

IEEE Trans. Computers, September, 2023

Algorithmic Obfuscation for LDPC Decoders.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2023

Fast and Low-Complexity Soft-Decision Generalized Integrated Interleaved Decoder.

[BibT_eX]

[DOI]

IEEE J. Sel. Areas Inf. Theory, 2023

Dimensions of Channel Coding: From Theory to Algorithms to Applications.

[BibT_eX]

[DOI]

IEEE J. Sel. Areas Inf. Theory, 2023

2022

Polynomial Multiplication Architecture with Integrated Modular Reduction for R-LWE Cryptosystems.

[BibT_eX]

[DOI]

Zheang Huai

J. Signal Process. Syst., 2022

Efficient Hardware Implementation Architectures for Long Integer Modular Multiplication over General Solinas Prime.

[BibT_eX]

[DOI]

Zheang Huai

J. Signal Process. Syst., 2022

Low-Latency Nested Decoding for Short Generalized Integrated Interleaved BCH Codes.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2022

Efficient Sub-Codeword Key Equation Solver for Generalized Integrated Interleaved BCH Decoder.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2022

Low-Complexity Resource-Shareable Parallel Generalized Integrated Interleaved Encoder.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Fast En/Decoding of Reed-Solomon Codes for Failure Recovery.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2022

A Survey on High-Throughput Non-Binary LDPC Decoders: ASIC, FPGA, and GPU Architectures.

[BibT_eX]

[DOI]

Oscar Ferraz

Srinivasan Subramaniyan

IEEE Commun. Surv. Tutorials, 2022

Efficient Reconfigurable Vandermonde Matrix Inverter for Erasure-Correcting Generalized Integrated Interleaved Decoding.

[BibT_eX]

[DOI]

Proceedings of the IEEE Workshop on Signal Processing Systems, 2022

Low-Complexity AES Architectures Resilient to Power Analysis Attacks.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Efficient Check Node Processing for Min-Max NB-LDPC Decoding over Lower-Order Finite Fields.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Efficient Nested Key Equation Solver for Short Generalized Integrated Interleaved BCH Codes.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Improved Miscorrection Detection for Generalized Integrated Interleaved BCH Codes.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Communications, 2022

2021

Generalized SAT-Attack-Resistant Logic Locking.

[BibT_eX]

[DOI]

IEEE Trans. Inf. Forensics Secur., 2021

Fast Nested Key Equation Solvers for Generalized Integrated Interleaved Decoder.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Special Section on Edge AI and Accelerators.

[BibT_eX]

[DOI]

Deepu John

Yongfu Li

IEEE Open J. Circuits Syst., 2021

Miscorrection Mitigation for Generalized Integrated Interleaved BCH Codes.

[BibT_eX]

[DOI]

IEEE Commun. Lett., 2021

Low-Latency VLSI Architectures for Modular Polynomial Multiplication via Fast Filtering and Applications to Lattice-Based Cryptography.

[BibT_eX]

[DOI]

CoRR, 2021

An Efficient Parallel Architecture for Resource-Shareable Reed-Solomon Encoder.

[BibT_eX]

[DOI]

Proceedings of the IEEE Workshop on Signal Processing Systems, 2021

Efficient Architecture for Long Integer Modular Multiplication over Solinas Prime.

[BibT_eX]

[DOI]

Zheang Huai

Proceedings of the IEEE Workshop on Signal Processing Systems, 2021

A Low-Complexity Flexible Logic-Locking Scheme Resisting Removal Attacks.

[BibT_eX]

[DOI]

Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

Low-Complexity Parallel Cyclic Redundancy Check.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Reduced-Complexity Modular Polynomial Multiplication for R-LWE Cryptosystems.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 2021

Scaled Fast Nested Key Equation Solver for Generalized Integrated Interleaved BCH Decoders.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 2021

Pipelined High-Throughput NTT Architecture for Lattice-Based Cryptography.

[BibT_eX]

[DOI]

Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2021

2020

Efficient VLSI Architectures for Coupled-Layered Regenerating Codes.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2020

Reduced-Complexity Key Equation Solvers for Generalized Integrated Interleaved BCH Decoders.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst., 2020

Scaled Nested Key Equation Solver for Generalized Integrated Interleaved Decoder.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst., 2020

VLSI Architectures for Reed-Solomon Codes: Classic, Nested, Coupled, and Beyond.

[BibT_eX]

[DOI]

IEEE Open J. Circuits Syst., 2020

Low-Complexity Architectures for Parallel Long BCH Encoders.

[BibT_eX]

[DOI]

Proceedings of the IEEE Workshop on Signal Processing Systems, 2020

Efficient Nested Key Equation Solver Architectures for Generalized Integrated Interleaved Codes.

[BibT_eX]

[DOI]

Proceedings of the Information Theory and Applications Workshop, 2020

A New Logic-Locking Scheme Resilient to Gate Removal Attack.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

High-Speed and Low-Complexity Parallel Long BCH Encoder.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019

Efficient Architectures for Generalized Integrated Interleaved Decoder.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A Low-Power Parallel Architecture for Linear Feedback Shift Registers.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2019

On the Construction of Composite Finite Fields for Hardware Obfuscation.

[BibT_eX]

[DOI]

Yingjie Lao

IEEE Trans. Computers, 2019

Relaxing the Constraints on Locally Recoverable Erasure Codes by Finite Field Element Variation.

[BibT_eX]

[DOI]

IEEE Commun. Lett., 2019

Side Channel Attack Resistant AES Design Based on Finite Field Construction Variation.

[BibT_eX]

[DOI]

Phillip Shvartsman

Proceedings of the 2019 IEEE International Workshop on Signal Processing Systems, 2019

Decoding of Generalized Three-Layer Integrated Interleaved Codes.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Information Theory, 2019

Reducing Parallel Linear Feedback Shift Register Complexity Through Input Tap Modification.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Hardware Obfuscation of AES through Finite Field Construction Variation.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Hardware Obfuscation Through Reconfiguration Finite Field Arithmetic Units.

[BibT_eX]

[DOI]

Ankur A Sharma

Yingjie Lao

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Systematic Encoder of Generalized Three-Layer Integrated Interleaved Codes.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE International Conference on Communications, 2019

2018

Generalized Three-Layer Integrated Interleaved Codes.

[BibT_eX]

[DOI]

IEEE Commun. Lett., 2018

Ultra-Compressed Three-Error-Correcting BCH Decoder.

[BibT_eX]

[DOI]

Michael O'Sullivan

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Perfect Column-Layered Two-Bit Message-Passing LDPC Decoder and Architectures.

[BibT_eX]

[DOI]

Alexander Bazarsky

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017

Low-Complexity Transformed Encoder Architectures for Quasi-Cyclic Nonbinary LDPC Codes Over Subfields.

[BibT_eX]

[DOI]

Ying Tai

IEEE Trans. Very Large Scale Integr. Syst., 2017

Modified Generalized Integrated Interleaved Codes for Local Erasure Recovery.

[BibT_eX]

[DOI]

IEEE Commun. Lett., 2017

2016

A Flexible and Low-Complexity Local Erasure Recovery Scheme.

[BibT_eX]

[DOI]

Steven Sprouse

Ishai Ilani

IEEE Commun. Lett., 2016

Low-power partial-parallel Chien search architecture with polynomial degree reduction.

[BibT_eX]

[DOI]

Itai Dror

Sanel Alterman

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015

Low-Complexity Modified Trellis-Based Min-Max Non- Binary LDPC Decoders.

[BibT_eX]

[DOI]

J. Commun., 2015

Modified trellis-based Min-max decoder for non-binary LDPC codes.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computing, Networking and Communications, 2015

2014

Efficient Check Node Processing Architectures for Non-binary LDPC Decoding Using Power Representation.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2014

Finite Alphabet Iterative Decoders for LDPC Codes: Optimization, Architecture and Analysis.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Interpolation-based Chase BCH decoder.

[BibT_eX]

[DOI]

Proceedings of the 2014 Information Theory and Applications Workshop, 2014

High-speed multi-block-row layered decoding for Quasi-cyclic LDPC codes.

[BibT_eX]

[DOI]

Ying Tai

Proceedings of the 2014 IEEE Global Conference on Signal and Information Processing, 2014

2013

Relaxed Min-Max Decoder Architectures for Nonbinary Low-Density Parity-Check Codes.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

Generalized Backward Interpolation for Algebraic Soft-Decision Decoding of Reed-Solomon Codes.

[BibT_eX]

[DOI]

IEEE Trans. Commun., 2013

An Efficient Interpolation-Based Chase BCH Decoder.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2013

Reducing the latency of Lee-O'Sullivan interpolation through modified initialization.

[BibT_eX]

[DOI]

Richard Shi

James A. Ritcey

Proceedings of the 2013 Information Theory and Applications Workshop, 2013

Low-power design of Reed-Solomon encoders.

[BibT_eX]

[DOI]

Jing Wang

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Low-energy and low-latency error-correction for phase change memory.

[BibT_eX]

[DOI]

M. P. Anantram

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Low-complexity finite alphabet iterative decoders for LDPC codes.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012

Efficient Generalized Minimum-distance Decoders of Reed-Solomon Codes.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2012

Modified Low-Complexity Chase Soft-Decision Decoder of Reed-Solomon Codes.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2012

Novel Interpolation and Polynomial Selection for Low-Complexity Chase Soft-Decision Reed-Solomon Decoding.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2012

Low-Complexity Reliability-Based Message-Passing Decoder Architectures for Non-Binary LDPC Codes.

[BibT_eX]

[DOI]

Shu Lin

IEEE Trans. Very Large Scale Integr. Syst., 2012

Efficient Reencoder Architectures for Algebraic Soft-Decision Reed-Solomon Decoding.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2012

Systematically Re-encoded Algebraic Soft-Decision Reed-Solomon Decoder.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2012

A Low-Complexity Three-Error-Correcting BCH Decoder for Optical Transport Network.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2012

On the implementation of modified fuzzy vault for biometric encryption.

[BibT_eX]

[DOI]

Richard Shi

James A. Ritcey

Proceedings of the 2012 Information Theory and Applications Workshop, 2012

Low complexity full parallel Multi-Split LDPC decoder reusing sign wire of row processor.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2012

Low-power LDPC decoding based on iteration prediction.

[BibT_eX]

[DOI]

Richard Shi

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Phase recovery for QPSK transmission without using complex multipliers.

[BibT_eX]

[DOI]

Jea Hack Lee

Myung Hoon Sunwoo

Proceedings of the 6th International Conference on Ubiquitous Information Management and Communication, 2012

A Chase-type Koetter-Vardy algorithm for soft-decision Reed-Solomon decoding.

[BibT_eX]

[DOI]

Yingquan Wu

Proceedings of the International Conference on Computing, Networking and Communications, 2012

Increasing the energy efficiency of WSNs using algebraic soft-decision reed-solomon decoders.

[BibT_eX]

[DOI]

Hao Wang

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

2011

Reduced-Complexity Decoder Architecture for Non-Binary LDPC Codes.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2011

Efficient Partial-Parallel Decoder Architecture for Quasi-Cyclic Nonbinary LDPC Codes.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Reliability-Driven ECC Allocation for Multiple Bit Error Resilience in Processor Cache.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2011

Reduced-complexity column-layered decoding and implementation for LDPC codes.

[BibT_eX]

[DOI]

Zhiqiang Cui

IET Commun., 2011

Efficient codeword recovery architecture for low-complexity Chase Reed-Solomon decoding.

[BibT_eX]

[DOI]

Proceedings of the Information Theory and Applications Workshop, 2011

A novel polynomial selection scheme for low-complexity chase algebraic soft-decision reed-solomon decoding.

[BibT_eX]

[DOI]

Yingquan Wu

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Low-complexity architectures for reliability-based message-passing non-binary LDPC decoding.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

An efficient architecture for iterative soft reliability-based majority-logic non-binary LDPC decoding.

[BibT_eX]

[DOI]

Proceedings of the Conference Record of the Forty Fifth Asilomar Conference on Signals, 2011

2010

Algebraic Soft-Decision Decoder Architectures for Long Reed-Solomon Codes.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2010

High-Throughput Interpolation Architecture for Algebraic Soft-Decision Reed-Solomon Decoding.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2010

Hardware complexities of algebraic soft-decision Reed-Solomon decoders and comparisons.

[BibT_eX]

[DOI]

Proceedings of the Information Theory and Applications Workshop, 2010

High-speed re-encoder design for algebraic soft-decision Reed-Solomon decoding.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Efficient architecture for generalized minimum-distance decoder of Reed-Solomon codes.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 2010

Partial-parallel decoder architecture for quasi-cyclic non-binary LDPC codes.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 2010

High-speed architecture for image reconstruction based on compressive sensing.

[BibT_eX]

[DOI]

Yang Chen

Proceedings of the IEEE International Conference on Acoustics, 2010

Reduced-latency scheduling scheme for min-max non-binary LDPC decoding.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2009

Backward Interpolation Architecture for Algebraic Soft-Decision Reed-Solomon Decoding.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2009

Factorization-free Low-complexity Chase Soft-decision Decoding of Reed-Solomon Codes.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008

Efficient VLSI Architecture for Soft-Decision Decoding of Reed-Solomon Codes.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2008

Efficient interpolration architecture for soft-decision Reed-Solomon decoding by applying slow-down.

[BibT_eX]

[DOI]

Proceedings of the IEEE Workshop on Signal Processing Systems, 2008

Error correction for multi-level NAND flash memory using Reed-Solomon codes.

[BibT_eX]

[DOI]

Bainan Chen

Proceedings of the IEEE Workshop on Signal Processing Systems, 2008

Novel interpolation architecture for Low-Complexity Chase soft-decision decoding of Reed-Solomon codes.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

FPGA implementation of a factorization processor for soft-decision reed-solomon decoding.

[BibT_eX]

[DOI]

Bainan Chen

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Combined interpolation architecture for soft-decision decoding of Reed-Solomon codes.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on Computer Design, 2008

Scalable interpolation architecture for soft-decision Reed-Solomon decoding.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

Efficient architecture for the Tate pairing in characteristic three.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

Efficient decoder design for high-throughput LDPC decoding.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

VLSi architecture design for algebraic soft-decision Reed-Solomon decoding.

[BibT_eX]

[DOI]

Proceedings of the 42nd Asilomar Conference on Signals, Systems and Computers, 2008

2007

Further Exploring the Strength of Prediction in the Factorization of Soft-Decision Reed-Solomon Decoding.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2007

MONET Special Issue on Next Generation Hardware Architectures for Secure Mobile Computing.

[BibT_eX]

[DOI]

Nicolas Sklavos

Máire McLoone

Mob. Networks Appl., 2007

Efficient Interpolation Architecture for Soft-Decision Reed-Solomon Decoding.

[BibT_eX]

[DOI]

Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

Low-complexity Interpolation Architecture for Soft-decision Reed-Solomon Decoding.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006

Reduced Complexity Interpolation Architecture for Soft-Decision Reed-Solomon Decoding.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2006

On the Optimum Constructions of Composite Field for the AES Algorithm.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2006

High-speed Factorization Architecture for Soft-decision Reed-Solomon Decoding.

[BibT_eX]

[DOI]

Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

Partial parallel factorization in soft-decision Reed-Solomon decoding.

[BibT_eX]

[DOI]

Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

2005

High-Speed Architectures for Parallel Long BCH Encoders.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2005

Fast factorization architecture in soft-decision Reed-Solomon decoding.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2005

2004

High-speed VLSI architectures for the AES algorithm.

[BibT_eX]

[DOI]