Xingyun Qi
According to our database1,
Xingyun Qi
authored at least 12 papers
between 2006 and 2024.
Collaborative distances:
Collaborative distances:
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On csauthors.net:
Bibliography
2024
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
2022
A 33.33 Gb/s/wire pin-efficient 1.06 pJ/bit wireline transceiver based on CNRZ-5 for Chiplet in 28 nm CMOS.
Microelectron. J., 2022
A CNRZ-7 Based Wireline Transceiver With High-Bandwidth-Density, Low-Power for D2D Communication.
IEEE Access, 2022
2021
Proceedings of the High Performance Computing - 36th International Conference, 2021
Proceedings of the Network and Parallel Computing, 2021
Proceedings of the 17th IFIP/IEEE International Symposium on Integrated Network Management, 2021
2020
MPLEG: A Multi-mode Physical Layer Error Generator for Link Layer Fault Tolerance Test.
Proceedings of the Advanced Computer Architecture - 13th Conference, 2020
Proceedings of the Advanced Computer Architecture - 13th Conference, 2020
2017
A Scalable and Resilient Microarchitecture Based on Multiport Binding for High-Radix Router Design.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium, 2017
2009
BOIN: A novel Bufferless Optical Interconnection Network for high performance computer.
Proceedings of the 7th IEEE/ACS International Conference on Computer Systems and Applications, 2009
Proceedings of the 8th IEEE/ACIS International Conference on Computer and Information Science, 2009
2006
Proceedings of the Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, 2006