Work-in-Process: Error-Compensation-Based Energy-Efficient MAC Unit for CNNs. - Xingyu Xu 008; Qingwen Wei; Yang Zhang; Hao Cai 001; Bo Liu 019 (CASES, 2023)

An Energy-Efficient MAC Design with Error Compensation Using Hybrid Approximate Logic Synthesis. - Qingwen Wei; Yang Zhang; Xingyu Xu 008; Hao Cai 001; Bo Liu 019 (ICTA, 2023)

FDCA: Fine-grained Digital-CIM based CNN Accelerator with Hybrid Quantization and Weight-Stationary Dataflow. - Bo Liu 019; Qingwen Wei; Yang Zhang; Xingyu Xu 008; Zihan Zou; Xinxiang Huang; Xin Si; Hao Cai 001 (DAC, 2024)

SUArch: Accelerating Layer-wise N: M Sparse Pattern with a Unified Architecture for Deep-learning Edge Device. - Xilong Kang; Qingwen Wei; Ningyuan Li 004; Xingyu Xu 008; Hao Cai 001; Bo Liu 019 (ASP-DAC, 2025)