Xingsheng Wang

Orcid: 0000-0001-8335-2033

Affiliations:
  • Huazhong University of Science and Technology, School of Optical and Electronic Information, Wuhan, China


According to our database1, Xingsheng Wang authored at least 17 papers between 2010 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2024
iPREFER: An Intelligent Parameter Extractor based on Features for BSIM-CMG Models.
CoRR, 2024

Multi-order Differential Neural Network for TCAD Simulation of the Semiconductor Devices.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

2023
Modeling and physical mechanism analysis of the effect of a polycrystalline-ferroelectric gate on FE-FinFETs.
Sci. China Inf. Sci., May, 2023

A comprehensive study of device variability of sub-5 nm nanosheet transistors and interplay with quantum confinement variation.
Sci. China Inf. Sci., February, 2023

Invited Paper: A Memristor-Based Stateful Majority-Inverter Graph Logic and 1-Bit Full Adder for In-Memory Computing Systems.
Proceedings of the IEEE International Conference on Integrated Circuits, 2023

2020
A TCAD-based Study of NDR Effect in NC-FinFET.
Proceedings of the 2020 IEEE International Conference on Integrated Circuits, 2020

Electrostatic Characteristics Analysis of Ferroelectric Tunneling Junctions with Different Structures.
Proceedings of the 2020 IEEE International Conference on Integrated Circuits, 2020

2019
A Novel General Compact Model Approach for 7nm Technology Node Circuit Optimization from Device Perspective and Beyond.
CoRR, 2019

2016
Nanowire transistor solutions for 5nm and beyond.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

2014
Accurate simulations of the interplay between process and statistical variability for nanoscale FinFET-based SRAM cell stability.
Proceedings of the 44th European Solid State Device Research Conference, 2014

2013
Statistical Variability and Reliability and the Impact on Corresponding 6T-SRAM Cell Design for a 14-nm Node SOI FinFET Technology.
IEEE Des. Test, 2013

SRAM device and cell co-design considerations in a 14nm SOI FinFET technology.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Impact of statistical variability and charge trapping on 14 nm SOI FinFET SRAM cell stability.
Proceedings of the European Solid-State Device Research Conference, 2013

2012
Statistical variability in 14-nm node SOI FinFETs and its impact on corresponding 6T-SRAM cell design.
Proceedings of the 2012 European Solid-State Device Research Conference, 2012

2011
New reliability mechanisms in memory design for sub-22nm technologies.
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

2010
Statistical-Variability Compact-Modeling Strategies for BSIM4 and PSP.
IEEE Des. Test Comput., 2010

Capturing intrinsic parameter fluctuations using the PSP compact model.
Proceedings of the Design, Automation and Test in Europe, 2010


  Loading...