Xing Huang

Orcid: 0000-0002-5396-110X

Affiliations:

Northwestern Polytechnical University, School of Computer Science, Xi'an, China
Technical University of Munich, Chair of Electronic Design Automation, Munich, Germany
Fuzhou University, College of Mathematics and Computer Science, Fuzhou, China (PhD 2018)

According to our database¹, Xing Huang authored at least 50 papers between 2013 and 2024.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

Legend:

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In proceedings

Article

PhD thesis

Dataset

Other

Bibliography

2024

A Robust Multilayer X-Architecture Global Routing System Based on Particle Swarm Optimization.

[BibT_eX]

[DOI]

IEEE Trans. Syst. Man Cybern. Syst., September, 2024

NR-Router+: Enhanced Non-Regular Electrode Routing With Optimal Pin Selection for Electrowetting-on-Dielectric Chips.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., September, 2024

Timing-Driven Obstacle-Avoiding X-Architecture Steiner Minimum Tree Algorithm With Slack Constraints.

[BibT_eX]

[DOI]

IEEE Trans. Syst. Man Cybern. Syst., May, 2024

Control-Logic Synthesis of Fully Programmable Valve Array Using Reinforcement Learning.

[BibT_eX]

[DOI]

Krishnendu Chakrabarty

Ulf Schlichtmann

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., January, 2024

Physical design for microfluidic biochips considering actual volume management and channel storage.

[BibT_eX]

[DOI]

Integr., 2024

Timing-Driven High-Level Synthesis for Continuous-Flow Microfluidic Biochips.

[BibT_eX]

[DOI]

Proceedings of the 25th International Symposium on Quality Electronic Design, 2024

Anomaly Detection Method based on Discrete Particle Swarm Optimization for Continuous-Flow Microfluidic Biochips.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

Error Recovery Method Based on Deep Reinforcement Learning for Fully Programmable Valve Array Biochips.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

Washing Optimization Method Based on Deep Reinforcement Learning for Fully Programmable Valve Array Biochips.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

PathDriver-Wash: A Path-Driven Wash Optimization Method for Continuous-Flow Lab-on-a-Chip Systems.

[BibT_eX]

[DOI]

Krishnendu Chakrabarty

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

Towards Automated Testing of Multiplexers in Fully Programmable Valve Array Biochips.

[BibT_eX]

[DOI]

Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

Adaptive Control-Logic Routing for Fully Programmable Valve Array Biochips Using Deep Reinforcement Learning.

[BibT_eX]

[DOI]

Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

2023

Enhanced Built-In Self-Diagnosis and Self-Repair Techniques for Daisy-Chain Design in MEDA Digital Microfluidic Biochips.

[BibT_eX]

[DOI]

Ling Zhang

Zipeng Li

Xing Huang

Krishnendu Chakrabarty

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., October, 2023

Application Mapping and Control-system Design for Microfluidic Biochips with Distributed Channel Storage.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., March, 2023

Design Automation for Continuous-Flow Lab-on-a-Chip Systems: A One-Pass Paradigm.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023

Fault-Tolerance-Oriented Physical Design for Fully Programmable Valve Array Biochips.

[BibT_eX]

[DOI]

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022

A Survey on Security of Digital Microfluidic Biochips: Technology, Attack, and Defense.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2022

VirtualSync+: Timing Optimization With Virtual Synchronization.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Contamination-Aware Synthesis for Programmable Microfluidic Devices.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Timing-Aware Layer Assignment for Advanced Process Technologies Considering via Pillars.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

PathDriver+: Enhanced Path-Driven Architecture Design for Flow-Based Microfluidic Biochips.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

MiniControl 2.0: Co-Synthesis of Flow and Control Layers for Microfluidic Biochips With Strictly Constrained Control Ports.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Flow-Based Microfluidic Biochips With Distributed Channel Storage: Synthesis, Physical Design, and Wash Optimization.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2022

Design automation for continuous-flow microfluidic biochips: A comprehensive review.

[BibT_eX]

[DOI]

Integr., 2022

Computer-aided Design Techniques for Flow-based Microfluidic Lab-on-a-chip Systems.

[BibT_eX]

[DOI]

Krishnendu Chakrabarty

Ulf Schlichtmann

ACM Comput. Surv., 2022

SPTA: A Scalable Parallel ILP-Based Track Assignment Algorithm with Two-Stage Partition.

[BibT_eX]

[DOI]

Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

LA-SVR: A High-Performance Layer Assignment Algorithm with Slew Violations Reduction.

[BibT_eX]

[DOI]

Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

NR-Router: Non-Regular Electrode Routing with Optimal Pin Selection for Electrowetting-on-Dielectric Chips.

[BibT_eX]

[DOI]

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021

DCSA: Distributed Channel-Storage Architecture for Flow-Based Microfluidic Biochips.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

BigIntegr: One-Pass Architectural Synthesis for Continuous-Flow Microfluidic Lab-on-a-Chip Systems.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

ALIFRouter: A Practical Architecture-Level Inter-FPGA Router for Logic Verification.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

An Efficient Programming Framework for Memristor-based Neuromorphic Computing.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020

Multicontrol: Advanced Control-Logic Synthesis for Flow-Based Microfluidic Biochips.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Timing-Driven Flow-Channel Network Construction for Continuous-Flow Microfluidic Biochips.

[BibT_eX]

[DOI]

Xing Huang

Tsung-Yi Ho

Krishnendu Chakrabarty

Wenzhong Guo

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

A Survey of DMFBs Security: State-of-the-Art Attack and Defense.

[BibT_eX]

[DOI]

Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

PathDriver: A Path-Driven Architectural Synthesis Flow for Continuous-Flow Microfluidic Biochips.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

MSFRoute: Multi-Stage FPGA Routing for Timing Division Multiplexing Technique.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

HTcatcher: Finite State Machine and Feature Verifcation for Large-scale Neuromorphic Computing Systems.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

MiniDelay: Multi-Strategy Timing-Aware Layer Assignment for Advanced Technology Nodes.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019

A Locating Method for Multi-Purposes HTs Based on the Boundary Network.

[BibT_eX]

[DOI]

IEEE Access, 2019

Open-Source Incubation Ecosystem for Digital Microfluidics - Status and Roadmap: Invited Paper.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2019

Physical Synthesis of Flow-Based Microfluidic Biochips Considering Distributed Channel Storage.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

MiniControl: Synthesis of Continuous-Flow Microfluidics with Strictly Constrained Control Ports.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2017

MLXR: multi-layer obstacle-avoiding X-architecture Steiner tree construction for VLSI routing.

[BibT_eX]

[DOI]

Sci. China Inf. Sci., 2017

2016

FH-OAOS: A Fast Four-Step Heuristic for Obstacle-Avoiding Octilinear Steiner Tree Construction.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2016

2015

Obstacle-Avoiding Algorithm in X-Architecture Based on Discrete Particle Swarm Optimization for VLSI Design.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2015

Multilayer Obstacle-Avoiding X-Architecture Steiner Minimal Tree Construction Based on Particle Swarm Optimization.

[BibT_eX]

[DOI]

IEEE Trans. Cybern., 2015

A PSO-based timing-driven Octilinear Steiner tree algorithm for VLSI routing considering bend reduction.

[BibT_eX]

[DOI]

Soft Comput., 2015

Fast obstacle-avoiding octilinear steiner minimal tree construction algorithm for VLSI design.

[BibT_eX]

[DOI]

Xing Huang

Wenzhong Guo

Guolong Chen

Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

2013

Obstacle-Avoiding Octagonal Steiner Tree construction based on Particle Swarm Optimization.

[BibT_eX]

[DOI]

Proceedings of the Ninth International Conference on Natural Computation, 2013

Xing Huang

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