Xinfeng Xie

Orcid: 0000-0001-7285-6682

According to our database1, Xinfeng Xie authored at least 27 papers between 2013 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Hierarchical Structured Neural Network for Retrieval.
CoRR, 2024

CoMERA: Computing- and Memory-Efficient Training via Rank-Adaptive Tensor Optimization.
CoRR, 2024

2023
MPU: Memory-centric SIMT Processor via In-DRAM Near-bank Computing.
ACM Trans. Archit. Code Optim., September, 2023

2022
Efficient In-DRAM Near-Bank Processing for Emerging Parallel Computing Workloads
PhD thesis, 2022

Rubik: A Hierarchical Architecture for Efficient Graph Neural Network Training.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

MPU-Sim: A Simulator for In-DRAM Near-Bank Processing Architectures.
IEEE Comput. Archit. Lett., 2022

A Transferable Approach for Partitioning Machine Learning Models on Multi-Chip-Modules.
Proceedings of the Fifth Conference on Machine Learning and Systems, 2022

2021
DLUX: A LUT-Based Near-Bank Accelerator for Data Center Deep Learning Training Workloads.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

MPU: Towards Bandwidth-abundant SIMT Processor via Near-bank Computing.
CoRR, 2021

SpaceA: Sparse Matrix Vector Multiplication on Processing-in-Memory Accelerator.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021

SEALing Neural Network Models in Encrypted Deep Learning Accelerators.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020
NNBench-X: A Benchmarking Methodology for Neural Network Accelerator Designs.
ACM Trans. Archit. Code Optim., 2020

Rubik: A Hierarchical Architecture for Efficient Graph Learning.
CoRR, 2020

SEALing Neural Network Models in Secure Deep Learning Accelerators.
CoRR, 2020

SAGA-Bench: Software and Hardware Characterization of Streaming Graph Analytics Workloads.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2020

iPIM: Programmable In-Memory Image Processing Accelerator Using Near-Bank Architecture.
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

DeepSniffer: A DNN Model Extraction Framework Based on Learning Architectural Hints.
Proceedings of the ASPLOS '20: Architectural Support for Programming Languages and Operating Systems, 2020

2019
Neural Network Model Extraction Attacks in Edge Devices by Hearing Architectural Hints.
CoRR, 2019

QGAN: Quantized Generative Adversarial Networks.
CoRR, 2019

NNBench-X: Benchmarking and Understanding Neural Network Workloads for Accelerator Designs.
IEEE Comput. Archit. Lett., 2019

Analysis and Optimization of the Memory Hierarchy for Graph Processing Workloads.
Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019

Memory-Bound Proof-of-Work Acceleration for Blockchain Applications.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

FPSA: A Full System Stack Solution for Reconfigurable ReRAM-based NN Accelerator Architecture.
Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, 2019

2018
Exploiting Sparsity to Accelerate Fully Connected Layers of CNN-Based Applications on Mobile SoCs.
ACM Trans. Embed. Comput. Syst., 2018

HitNet: Hybrid Ternary Recurrent Neural Network.
Proceedings of the Advances in Neural Information Processing Systems 31: Annual Conference on Neural Information Processing Systems 2018, 2018

2017
Communication Optimization on GPU: A Case Study of Sequence Alignment Algorithms.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium, 2017

2013
The design and implementation of the multi-screen interaction service architecture for the Real-Time streaming media.
Proceedings of the Ninth International Conference on Natural Computation, 2013


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