Xin Yang

Affiliations:
  • Queen's University Belfast, ECIT Institute, Northern Ireland


According to our database1, Xin Yang authored at least 18 papers between 2006 and 2016.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2016
Feature study on a programmable network traffic classifier.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

2015
Per-flow state management technique for high-speed networks.
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015

Memory cost analysis for OpenFlow multiple table lookup.
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015

2014
A hardware acceleration scheme for memory-efficient flow processing.
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014

A configurable packet classification architecture for Software-Defined Networking.
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014

Optimized packet classification for Software-Defined Networking.
Proceedings of the IEEE International Conference on Communications, 2014

An improvement of IP address lookup based on rule filter analysis.
Proceedings of the IEEE International Conference on Communications, 2014

2012
Implementation of a network flow lookup circuit for next-generation packet classifiers.
Proceedings of the IEEE 25th International SOC Conference, 2012

2010
High-Performance random data lookup for network processing.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

2009
Design and Implementation of a Field Programmable CRC Circuit Architecture.
IEEE Trans. Very Large Scale Integr. Syst., 2009

DDR3 based lookup circuit for high-performance network processing.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

2008
A Scalable Packet Sorting Circuit for High-Speed WFQ Packet Scheduling.
IEEE Trans. Very Large Scale Integr. Syst., 2008

High performance IP lookup circuit using DDR SDRAM.
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

2007
A versatile content addressable memory architecture.
Proceedings of the 2007 IEEE International SOC Conference, 2007

Programmable CRC circuit architecture.
Proceedings of the 2007 IEEE International SOC Conference, 2007

Novel Content Addressable Memory Architecture for Adaptive Systems.
Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 2007

2006
A VLSI GFP Frame Delineation Circuit.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

High performance service-time-stamp computation for WFQ IP packet scheduling.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006


  Loading...