Xin Xin

Orcid: 0000-0002-6888-5218

Affiliations:
  • Xi'an University of Posts and Telecommunications, School of Electronics Engineering, China


According to our database1, Xin Xin authored at least 21 papers between 2017 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2024
An 11-bit Nyquist SAR-VCO Hybrid ADC with a Reused Ring-VCO for Power Reduction.
Circuits Syst. Signal Process., March, 2024

2023
A 14-bit 1-MS/s SAR ADC with a segmented capacitor array and background mismatch calibration for IoT sensing applications.
Microelectron. J., November, 2023

A Power-Efficient 13-Tap FIR Filter and an IIR Filter Embedded in a 10-Bit SAR ADC.
IEEE Trans. Circuits Syst. I Regul. Pap., 2023

2022
A 10-bit 100-MS/s SAR ADC With Always-On Reference Ripple Cancellation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

A 200 Hz-to-10 kHz bandwidth 11.83-ENOB level-crossing ADC with single continuous-time comparator.
Microelectron. J., 2022

A 0.6-V 12-bit 13.2-fJ/conversion-step SAR ADC with time-domain VCDL-based comparator and metastability immunity technique.
Microelectron. J., 2022

A 14-bit 1.2-V low power SAR ADC with digital background calibration in 0.18 μm CMOS.
Microelectron. J., 2022

A 0.6-V, 1.56-nW, 5.87-ppm/°C, 0.23%/V CMOS-Only Subthreshold Voltage Reference with the Threshold Voltage Difference.
Circuits Syst. Signal Process., 2022

High Energy Efficiency and Linearity Switching Scheme Without Reset Energy for SAR ADC.
Circuits Syst. Signal Process., 2022

2021
A chaos-based true random number generator based on OTA sharing and non-flipped folded Bernoulli mapping for high-precision ADC calibration.
Microelectron. J., 2021

A three-stage OTA with hybrid active miller enhanced compensation technique for large to heavy load applications.
Microelectron. J., 2021

A 1<sup>st</sup>-order noise shaping SAR ADC with dual-capacitor merge-and-split switching scheme for sensor chip.
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021

A 10-bit SAR ADC with adaptive VCO-based comparator for sensor chip.
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021

2020
A 10-bit 120-MS/s SAR ADC With Reference Ripple Cancellation Technique.
IEEE J. Solid State Circuits, 2020

A 10-Bit 100-MS/s SAR ADC with Always-on Reference Ripple Cancellation.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

A Power-Efficient 13-Tap FIR filter and an IIR Filter Embedded in a 10-bit SAR ADC.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2020

2018
LBFT: a fault-tolerant routing algorithm for load-balancing network-on-chip based on odd-even turn model.
J. Supercomput., 2018

A 750-nW 1-MHz 9-tap analog finite impulse response filter for wireless senor network chip.
Microelectron. J., 2018

2017
MCAR: Non-local adaptive Network-on-Chip routing with message propagation of congestion information.
Microprocess. Microsystems, 2017

Low-Cost Adaptive and Fault-Tolerant Routing Method for 2D Network-on-Chip.
IEICE Trans. Inf. Syst., 2017

Voltage-mode ultra-low power four quadrant multiplier using subthreshold PMOS.
IEICE Electron. Express, 2017


  Loading...