Xijiang Lin

According to our database, Xijiang Lin authored at least 60 papers between 1998 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

DFT for Complex Designs and Test Data Management.

Wu Yang, Jinshan Yu, Pearl He, Xijiang Lin

Proceedings of the IEEE International Test Conference in Asia, 2024

AI Driven Testing.

Yu Huang, Alex Yu, Louis Liu, Xijiang Lin

Proceedings of the IEEE International Test Conference in Asia, 2024

2021

Single Test Type to Replace Broadside and Skewed-Load Tests for Transition Faults.

Irith Pomeranz, Xijiang Lin

IEEE Trans. Very Large Scale Integr. Syst., 2021

Timing Critical Path Validation for Intel ATOM Cores Using Structural Test.

Wei Li, Shih-Yu Yang, Khen Wee, Ricardo Sanchez, Jay Desai, Kun-Han Tsai, Xijiang Lin

Proceedings of the 39th IEEE VLSI Test Symposium, 2021

On Modeling CMOS Library Cells for Cell Internal Fault Test Pattern Generation.

Xijiang Lin, Wu-Tung Cheng, Takeo Kobayashi, Andreas Glowatz

Proceedings of the 30th IEEE Asian Test Symposium, 2021

2020

Test Challenges of Intel IA Cores.

Uri Shpiro, Khen Wee, Kun-Han Tsai, Justyna Zawada, Xijiang Lin

Proceedings of the IEEE International Test Conference, 2020

2019

On Generating Fault Diagnosis Patterns for Designs with X Sources.

Xijiang Lin, Sudhakar M. Reddy

Proceedings of the 24th IEEE European Test Symposium, 2019

TEA: A Test Generation Algorithm for Designs with Timing Exceptions.

Naixing Wang, Chen Wang, Kun-Han Tsai, Wu-Tung Cheng, Xijiang Lin, Mark Kassab, Irith Pomeranz

Proceedings of the 28th IEEE Asian Test Symposium, 2019

2017

On applying scan based structural test for designs with dual-edge triggered flip-flops.

Xijiang Lin

Proceedings of the IEEE International Test Conference, 2017

Functional Broadside Test Generation Using a Commercial ATPG Tool.

Naixing Wang, Bo Yao, Xijiang Lin, Irith Pomeranz

Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

2016

Thermal-Aware Small-Delay Defect Testing in Integrated Circuits for Mitigating Overkill.

Dong Xiang, Kele Shen, Bhargab B. Bhattacharya, Xiaoqing Wen, Xijiang Lin

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Transistor stuck-on fault detection tests for digital CMOS circuits.

Xijiang Lin, Sudhakar M. Reddy, Janusz Rajski

Proceedings of the 21th IEEE European Test Symposium, 2016

On Achieving Maximal Chain Diagnosis Resolution through Test Pattern Selection.

Xijiang Lin, Sudhakar M. Reddy, Wu-Tung Cheng

Proceedings of the 25th IEEE Asian Test Symposium, 2016

2015

Using Boolean Tests to Improve Detection of Transistor Stuck-Open Faults in CMOS Digital Logic Circuits.

Xijiang Lin, Sudhakar M. Reddy, Janusz Rajski

Proceedings of the 28th International Conference on VLSI Design, 2015

On generating high quality tests based on cell functions.

Xijiang Lin, Sudhakar M. Reddy

Proceedings of the 2015 IEEE International Test Conference, 2015

On Improving Transition Test Set Quality to Detect CMOS Transistor Stuck-Open Faults.

Xijiang Lin, Wu-Tung Cheng, Janusz Rajski

Proceedings of the 24th IEEE Asian Test Symposium, 2015

2014

Using dynamic shift to reduce test data volume in high-compression designs.

Xijiang Lin, Mark Kassab, Janusz Rajski

Proceedings of the 19th IEEE European Test Symposium, 2014

Timing-Aware ATPG.

Mark Kassab, Benoit Nadeau-Dostie, Xijiang Lin

Proceedings of the Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits., 2014

2013

Test compaction for small-delay defects using an effective path selection scheme.

Dong Xiang, Jianbo Li, Krishnendu Chakrabarty, Xijiang Lin

ACM Trans. Design Autom. Electr. Syst., 2013

Multicycle-aware At-speed Test Methodology.

Kun-Han Tsai, Xijiang Lin

Proceedings of the 22nd Asian Test Symposium, 2013

2012

On Utilizing Test Cube Properties to Reduce Test Data Volume Further.

Xijiang Lin, Janusz Rajski

Proceedings of the 21st IEEE Asian Test Symposium, 2012

Power Supply Droop and Its Impacts on Structural At-Speed Testing.

Xijiang Lin

Proceedings of the 21st IEEE Asian Test Symposium, 2012

2011

Low power testing - What can commercial DFT tools provide?

Xijiang Lin

Proceedings of the 2011 International Green Computing Conference and Workshops, 2011

Power Aware Embedded Test.

Xijiang Lin, Elham K. Moghaddam, Nilanjan Mukherjee, Benoit Nadeau-Dostie, Janusz Rajski, Jerzy Tyszer

Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010

On Reducing Scan Shift Activity at RTL.

Elif Alpaslan, Yu Huang, Xijiang Lin, Wu-Tung Cheng, Jennifer Dworak

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Clock control architecture and ATPG for reducing pattern count in SoC designs with multiple clock domains.

Tom Waayers, Richard Morren, Xijiang Lin, Mark Kassab

Proceedings of the 2011 IEEE International Test Conference, 2010

Detecting and diagnosing open defects.

Dat Tran, LeRoy Winemberg, Darrell Carder, Xijiang Lin, Joe LeBritton, Bruce Swanson

Proceedings of the 2011 IEEE International Test Conference, 2010

Low capture power at-speed test in EDT environment.

Elham K. Moghaddam, Janusz Rajski, Sudhakar M. Reddy, Xijiang Lin, Nilanjan Mukherjee, Mark Kassab

Proceedings of the 2011 IEEE International Test Conference, 2010

Adaptive Low Shift Power Test Pattern Generator for Logic BIST.

Xijiang Lin, Janusz Rajski

Proceedings of the 19th IEEE Asian Test Symposium, 2010

2009

Low-Power Scan Operation in Test Compression Environment.

Dariusz Czysz, Mark Kassab, Xijiang Lin, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Test Generation for Designs with On-Chip Clock Generators.

Xijiang Lin, Mark Kassab

Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008

Scan Shift Power Reduction by Freezing Power Sensitive Scan Cells.

Xijiang Lin, Yu Huang

J. Electron. Test., 2008

Reducing Scan Shift Power at RTL.

Elif Alpaslan, Yu Huang, Xijiang Lin, Wu-Tung Cheng, Jennifer Dworak

Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

Test Generation for Interconnect Opens.

Xijiang Lin, Janusz Rajski

Proceedings of the 2008 IEEE International Test Conference, 2008

Low Power Scan Shift and Capture in the EDT Environment.

Dariusz Czysz, Mark Kassab, Xijiang Lin, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer

Proceedings of the 2008 IEEE International Test Conference, 2008

Test Power Reduction by Blocking Scan Cell Outputs.

Xijiang Lin, Janusz Rajski

Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007

Scan-Based Tests with Low Switching Activity.

Santiago Remersaro, Xijiang Lin, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski

IEEE Des. Test Comput., 2007

Low Shift and Capture Power Scan Tests.

Santiago Remersaro, Xijiang Lin, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Test Generation for Timing-Critical Transition Faults.

Xijiang Lin, Mark Kassab, Janusz Rajski

Proceedings of the 16th Asian Test Symposium, 2007

Programmable Logic BIST for At-speed Test.

Yu Huang, Xijiang Lin

Proceedings of the 16th Asian Test Symposium, 2007

2006

Scan Tests with Multiple Fault Activation Cycles for Delay Faults.

Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Xijiang Lin, Janusz Rajski

Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

The Impacts of Untestable Defects on Transition Fault Testing.

Xijiang Lin, Janusz Rajski

Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs.

Santiago Remersaro, Xijiang Lin, Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski

Proceedings of the 2006 IEEE International Test Conference, 2006

Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects.

Xijiang Lin, Kun-Han Tsai, Chen Wang, Mark Kassab, Janusz Rajski, Takeo Kobayashi, Randy Klingenberg, Yasuo Sato, Shuji Hamada, Takashi Aikyo

Proceedings of the 15th Asian Test Symposium, 2006

2005

Measures to Improve Delay Fault Testing on Low-Cost Testers - A Case Study.

Matthias Beck, Olivier Barondeau, Frank Poehl, Xijiang Lin, Ron Press

Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality.

Matthias Beck, Olivier Barondeau, Martin Kaibel, Frank Poehl, Xijiang Lin, Ron Press

Proceedings of the 2005 Design, 2005

Propagation delay fault: a new fault model to test delay faults.

Xijiang Lin, Janusz Rajski

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2003

High-Frequency, At-Speed Scan Testing.

Xijiang Lin, Ron Press, Janusz Rajski, Paul Reuter, Thomas Rinderknecht, Bruce Swanson, Nagesh Tamarapalli

IEEE Des. Test Comput., 2003

Test generation for designs with multiple clocks.

Xijiang Lin, Rob Thompson

Proceedings of the 40th Design Automation Conference, 2003

2002

Novel Techniques for Achieving High At-Speed Transition Fault Test Coverage for Motorola's Microprocessors Based on PowerPC(tm) Instruction Set Architecture.

Nandu Tendolkar, Rajesh Raina, Rick Woltenberg, Xijiang Lin, Bruce Swanson, Greg Aldrich

Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Conflict driven techniques for improving deterministic test pattern generation.

Chen Wang, Sudhakar M. Reddy, Irith Pomeranz, Xijiang Lin, Janusz Rajski

Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

2001

On static test compaction and test pattern ordering for scan designs.

Xijiang Lin, Janusz Rajski, Irith Pomeranz, Sudhakar M. Reddy

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Experimental Results of Forward-Looking Reverse Order Fault Simulation on Industrial Circuits with Scan.

Irith Pomeranz, Sudhakar M. Reddy, Xijiang Lin

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

2000

SIFAR: Static Test Compaction for Synchronous Sequential Circuits Based on Single Fault Restoration.

Xijiang Lin, Wu-Tung Cheng, Irith Pomeranz, Sudhakar M. Reddy

Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

1999

Procedures for Identifying Undetectable and Redundant Faults In Synchronous Sequential Circuits.

Sudhakar M. Reddy, Irith Pomeranz, Nadir Z. Basturkmen, Xijiang Lin

Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

Techniques for improving the efficiency of sequential circuit test generation.

Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy

Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Full Scan Fault Coverage With Partial Scan.

Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy

Proceedings of the 1999 Design, 1999

1998

On Removing Redundant Faults in Synchronous Sequential Circuits.

Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy

Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

MIX: A Test Generation System for Synchronous Sequential Circuits.

Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy

Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

On finding undetectable and redundant faults in synchronous sequential circuits.

Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy

Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998