Xiaoyong Xue
Orcid: 0000-0001-7534-1190
According to our database1,
Xiaoyong Xue
authored at least 63 papers
between 2010 and 2024.
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Bibliography
2024
A 28-nm 36 Kb SRAM CIM Engine With 0.173 μm<sup>2</sup> 4T1T Cell and Self-Load-0 Weight Update for AI Inference and Training Applications.
IEEE J. Solid State Circuits, October, 2024
SET Tolerable SRAM Hardened by DMR Circuit With Feedback-Split-Gate Voter and High-Speed Hierarchical Structure.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2024
Optimal Solution Guided Branching Strategy for Neural Network Branch and Bound Verification.
Proceedings of the Engineering of Complex Computer Systems - 28th International Conference, 2024
A Heuristic and Greedy Weight Remapping Scheme with Hardware Optimization for Irregular Sparse Neural Networks Implemented on CIM Accelerator in Edge AI Applications.
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024
2023
Tempo-CIM: A RRAM Compute-in-Memory Neuromorphic Accelerator With Area-Efficient LIF Neuron and Split-Train-Merged-Inference Algorithm for Edge AI Applications.
IEEE J. Emerg. Sel. Topics Circuits Syst., December, 2023
J. Syst. Archit., November, 2023
An Emerging NVM CIM Accelerator With Shared-Path Transpose Read and Bit-Interleaving Weight Storage for Efficient On-Chip Training in Edge Devices.
IEEE Trans. Circuits Syst. II Express Briefs, July, 2023
IEEE Trans. Circuits Syst. II Express Briefs, June, 2023
ARBiS: A Hardware-Efficient SRAM CIM CNN Accelerator With Cyclic-Shift Weight Duplication and Parasitic-Capacitance Charge Sharing for AI Edge Application.
IEEE Trans. Circuits Syst. I Regul. Pap., January, 2023
A 1T2R1C ReRAM CIM Accelerator With Energy-Efficient Voltage Division and Capacitive Coupling for CNN Acceleration in AI Edge Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2023
Proceedings of the 23rd IEEE International Conference on Software Quality, 2023
A 9Mb HZO-Based Embedded FeRAM with 10<sup>12</sup>-Cycle Endurance and 5/7ns Read/Write using ECC-Assisted Data Refresh and Offset-Canceled Sense Amplifier.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
NBSSN: A Neuromorphic Binary Single-Spike Neural Network for Efficient Edge Intelligence.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Proceedings of the Formal Methods and Software Engineering, 2023
Proceedings of the Fundamentals of Software Engineering - 10th International Conference, 2023
2022
A 2D2R ReRAM CIM accelerator for multilayer perceptron in visual classification applications.
Microelectron. J., 2022
A 28 nm 512 Kb adjacent 2T2R RRAM PUF with interleaved cell mirroring and self-adaptive splitting for high density and low BER cryptographic key in IoT devices.
Microelectron. J., 2022
A 28 nm 81 Kb 59-95.3 TOPS/W 4T2R ReRAM Computing-in-Memory Accelerator With Voltage-to-Time-to-Digital Based Output.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022
Proceedings of the Dependable Software Engineering. Theories, Tools, and Applications, 2022
NIMBLE: A Neuromorphic Learning Scheme and Memristor Based Computing-in-Memory Engine for EMG Based Hand Gesture Recognition.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
2021
An Energy Efficient Computing-in-Memory Accelerator With 1T2R Cell and Fully Analog Processing for Edge AI Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
High-Density 3-D Stackable Crossbar 2D2R nvTCAM With Low-Power Intelligent Search for Fast Packet Forwarding in 5G Applications.
IEEE J. Solid State Circuits, 2021
Integr., 2021
24.2 A 14nm-FinFET 1Mb Embedded 1T1R RRAM with a 0.022µ m<sup>2</sup> Cell Size Using Self-Adaptive Delayed Termination and Multi-Cell Reference.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Intra-array Non-Idealities Modeling and Algorithm Optimization for RRAM-based Computing-in-Memory Applications.
Proceedings of the 14th IEEE International Conference on ASIC, 2021
Proceedings of the 14th IEEE International Conference on ASIC, 2021
Proceedings of the 14th IEEE International Conference on ASIC, 2021
Proceedings of the 14th IEEE International Conference on ASIC, 2021
Algorithm/Hardware Co-Design Configurable SAR ADC with Low Power for Computing-in-Memory in 28nm CMOS.
Proceedings of the 14th IEEE International Conference on ASIC, 2021
2020
IEEE Trans. Very Large Scale Integr. Syst., 2020
A 28nm 1.5Mb Embedded 1T2R RRAM with 14.8 Mb/mm<sup>2</sup> using Sneaking Current Suppression and Compensation Techniques.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
A Parallel Change Detection Method for Spatiotemporally Multi-Temporal SAR Image Based On Enhance Learning and Wavelet.
Proceedings of the 13th International Symposium on Computational Intelligence and Design, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2019
A 0.75 V reference clamping sense amplifier for low-power high-density ReRAM with dynamic pre-charge technique.
IEICE Electron. Express, 2019
A 28nm 512Kb adjacent 2T2R RRAM PUF with interleaved cell mirroring and self-adaptive splitting for extremely low bit error rate of cryptographic key.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019
A High Reliability 500 µW Resistance-to-Digital Interface Circuit for SnO2 Gas Sensor IoT Applications.
Proceedings of the 13th IEEE International Conference on ASIC, 2019
Nonvolatile Binary CNN Accelerator with Extremely Low Standby Power using RRAM for IoT Applications.
Proceedings of the 13th IEEE International Conference on ASIC, 2019
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2019
2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
A Physically Unclonable Function with BER < 0.35% for Secure Chip Authentication Using Write Speed Variation of RRAM.
Proceedings of the 48th European Solid-State Device Research Conference, 2018
Nonvolatile Crossbar 2D2R TCAM with Cell Size of 16.3 F<sup>2</sup> and K-means Clustering for Power Reduction.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
2017
Dynamic Data-Dependent Reference to Improve Sense Margin and Speed of Magnetoresistive Random Access Memory.
IEEE Trans. Circuits Syst. II Express Briefs, 2017
Proceedings of the 2017 IEEE SmartWorld, 2017
A small area and low power true random number generator using write speed variation of oxidebased RRAM for IoT security application.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the 12th IEEE International Conference on ASIC, 2017
ReRAM write circuit with dynamic uniform and small overshoot compliance current under PVT variations.
Proceedings of the 12th IEEE International Conference on ASIC, 2017
2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
IEEE Trans. Circuits Syst. II Express Briefs, 2016
IEICE Electron. Express, 2016
Proceedings of the 2016 IEEE International Conference on Internet of Things (iThings) and IEEE Green Computing and Communications (GreenCom) and IEEE Cyber, 2016
Novel 3D horizontal RRAM architecture with isolation cell structure for sneak current depression.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
A compact pico-second in-situ sensor using programmable ring oscillators for advanced on chip variation characterization in 28nm HKMG.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
2015
3D vertical RRAM architecture and operation algorithms with effective IR-drop suppressing and anti-disturbance.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Impacts of external magnetic field and high temperature disturbance on MRAM reliability based on FPGA test platform.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
A low cost and high reliability true random number generator based on resistive random access memory.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
2013
A 0.13 µm 8 Mb Logic-Based Cu<sub>x</sub> Si<sub>y</sub> O ReRAM With Self-Adaptive Operation for Yield Enhancement and Power Reduction.
IEEE J. Solid State Circuits, 2013
A 2Mb ReRAM with two bits error correction codes circuit for high reliability application.
Proceedings of the IEEE 10th International Conference on ASIC, 2013
2012
64Kb logic RRAM chip resisting physical and side-channel attacks for encryption keys storage.
IEICE Electron. Express, 2012
A 0.13µm 8Mb logic based CuxSiyO resistive memory with self-adaptive yield enhancement and operation power reduction.
Proceedings of the Symposium on VLSI Circuits, 2012
2011
IEICE Electron. Express, 2011
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011
2010