Xiaoyao Liang

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

A sharing-aware L1.5D cache for data reuse in GPGPUs.

[BibT_eX]

[DOI]

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

HUBPA: high utilization bidirectional pipeline architecture for neuromorphic computing.

[BibT_eX]

[DOI]

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018

IBOM: An Integrated and Balanced On-Chip Memory for High Performance GPGPUs.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2018

CNFET-Based High Throughput SIMD Architecture.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Approximate Random Dropout.

[BibT_eX]

[DOI]

CoRR, 2018

Invocation-driven neural approximate computing with a multiclass-classifier and multiple approximators.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2018

AXNet: approximate computing using an end-to-end trainable neural network.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2018

A FPGA Friendly Approximate Computing Framework with Hybrid Neural Networks: (Abstract Only).

[BibT_eX]

[DOI]

Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

In-growth test for monolithic 3D integrated SRAM.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017

Bank Stealing for a Compact and Efficient Register File Architecture in GPGPU.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

A Hint Frequency Based Approach to Enhancing the I/O Performance of Multilevel Cache Storage Systems.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2017

Incorporating selective victim cache into GPGPU for high-performance computing.

[BibT_eX]

[DOI]

Concurr. Comput. Pract. Exp., 2017

Fault clustering technique for 3D memory BISR.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Accelerator-friendly neural-network training: Learning variations and defects in RRAM crossbar.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

On Quality Trade-off Control for Approximate Computing Using Iterative Training.

[BibT_eX]

[DOI]

Proceedings of the 54th Annual Design Automation Conference, 2017

Sneak-Path Based Test and Diagnosis for 1R RRAM Crossbar Using Voltage Bias Technique.

[BibT_eX]

[DOI]

Proceedings of the 54th Annual Design Automation Conference, 2017

2016

A Learning Algorithm for Bayesian Networks and Its Efficient Implementation on GPUs.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2016

A Novel Test Method for Metallic CNTs in CNFET-Based SRAMs.

[BibT_eX]

[DOI]

Naifeng Jing

Li Jiang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Energy-Efficient eDRAM-Based On-Chip Storage Architecture for GPGPUs.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2016

Cache-emulated register file: An integrated on-chip memory architecture for high performance GPGPUs.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

Defect tolerance for CNFET-based SRAMs.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Test Conference, 2016

Applying Victim Cache in High Performance GPGPU Computing.

[BibT_eX]

[DOI]

Proceedings of the 15th International Symposium on Parallel and Distributed Computing, 2016

Power Attack Defense: Securing Battery-Backed Data Centers.

[BibT_eX]

[DOI]

Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

CNFET-based high throughput register file architecture.

[BibT_eX]

[DOI]

Proceedings of the 34th IEEE International Conference on Computer Design, 2016

2015

Efficient graph computation on hybrid CPU and GPU systems.

[BibT_eX]

[DOI]

J. Supercomput., 2015

Buddy SM: Sharing Pipeline Front-End for Improved Energy Efficiency in GPGPUs.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2015

Timing-driven placement for carbon nanotube circuits.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE International System-on-Chip Conference, 2015

On microarchitectural modeling for CNFET-based circuits.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE International System-on-Chip Conference, 2015

On diagnosable and tunable 3D clock network design for lifetime reliability enhancement.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Test Conference, 2015

CGSharing: Efficient content sharing in GPU-based cloud gaming.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

Bank stealing for conflict mitigation in GPGPU Register File.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

Towards sustainable in-situ server systems in the big data era.

[BibT_eX]

[DOI]

Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015

Building Fuel Powered Supercomputing Data Center at Low Cost.

[BibT_eX]

[DOI]

Proceedings of the 29th ACM on International Conference on Supercomputing, 2015

Exploring Hardware Profile-Guided Green Datacenter Scheduling.

[BibT_eX]

[DOI]

Proceedings of the 44th International Conference on Parallel Processing, 2015

A novel TSV probing technique with adhesive test interposer.

[BibT_eX]

[DOI]

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Jump test for metallic CNTs in CNFET-based SRAM.

[BibT_eX]

[DOI]

Feng Xie

Qiang Xu

Naifeng Jing

Li Jiang

Proceedings of the 52nd Annual Design Automation Conference, 2015

2014

HFA: A Hint Frequency-based approach to enhance the I/O performance of multi-level cache storage systems.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE International Conference on Parallel and Distributed Systems, 2014

Dynamic front-end sharing in graphics processing units.

[BibT_eX]

[DOI]

Tao Zhang

Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

2013

Compiler assisted dynamic register file in GPGPU.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

An energy-efficient and scalable eDRAM-based register file architecture for GPGPU.

[BibT_eX]

[DOI]

Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013

2012

AgileRegulator: A hybrid voltage regulator scheme redeeming dark silicon for power efficiency in a multicore architecture.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012

2011

MicroFix: Using timing interpolation and delay sensors for power reduction.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2011

2010

Leveraging the core-level complementary effects of PVT variations to reduce timing emergencies in multi-core processors.

[BibT_eX]

[DOI]

Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), 2010

2009

Revival: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency.

[BibT_eX]

[DOI]

Gu-Yeon Wei

IEEE Micro, 2009

MicroFix: exploiting path-grained timing adaptability for improving power-performance efficiency.

[BibT_eX]

[DOI]

Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

Empirical performance models for 3T1D memories.

[BibT_eX]

[DOI]

Proceedings of the 27th International Conference on Computer Design, 2009

Design and test strategies for microarchitectural post-fabrication tuning.

[BibT_eX]

[DOI]

Proceedings of the 27th International Conference on Computer Design, 2009

2008

Replacing 6T SRAMs with 3T1D DRAMs in the L1 Data Cache to Combat Process Variability.

[BibT_eX]

[DOI]

IEEE Micro, 2008

A Process-Variation-Tolerant Floating-Point Unit with Voltage Interpolation and Variable Latency.

[BibT_eX]

[DOI]

Gu-Yeon Wei

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

Instruction-driven clock scheduling with glitch mitigation.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

2007

Process Variation Tolerant 3T1D-Based Cache Architectures.

[BibT_eX]

[DOI]

Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-40 2007), 2007

Architectural power models for SRAM and CAM structures based on hybrid analytical/empirical techniques.

[BibT_eX]

[DOI]

Kerem Turgay

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

2006

Mitigating the Impact of Process Variations on Processor Register Files and Execution Units.

[BibT_eX]

[DOI]

Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 2006

Microarchitecture parameter selection to optimize system performance under process variation.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

2005

Dynamic coarse grain dataflow reconfiguration technique for real-time systems design.

[BibT_eX]

[DOI]

Akshay Athalye

Sangjin Hong

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Equalizing data-path for processing speed determination in block level pipelining.

[BibT_eX]

[DOI]