Xiaowen Wu

According to our database1, Xiaowen Wu authored at least 46 papers between 1997 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2023
The Weighted, Relaxed Gradient-Based Iterative Algorithm for the Generalized Coupled Conjugate and Transpose Sylvester Matrix Equations.
Axioms, November, 2023

Simulating Temporally and Spatially Correlated Wind Speed Time Series by Spectral Representation Method.
Complex Syst. Model. Simul., 2023

2021
Test and Calculation of the Total Electrical Field at Ground Level for ±500kV HVDC Overhead Transmission Line.
Proceedings of the CONF-CDS 2021: The 2nd International Conference on Computing and Data Science, 2021

2018
A segmented attitude planning and controlling method for agile satellite based on Pseudospectral method.
Trans. Inst. Meas. Control, 2018

2016
JADE: a Heterogeneous Multiprocessor System Simulation Platform Using Recorded and Statistical Application Models.
Proceedings of the 1st International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems, 2016

2015
An Inter/Intra-Chip Optical Network for Manycore Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Actively Alleviate Power Gating-Induced Power/Ground Noise Using Parasitic Capacitance of On-Chip Memories in MPSoC.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Crosstalk Noise in WDM-Based Optical Networks-on-Chip: A Formal Study and Comparison.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Fat-Tree-Based Optical Interconnection Networks Under Crosstalk Noise Constraint.
IEEE Trans. Very Large Scale Integr. Syst., 2015

An Analytical Study of Power Delivery Systems for Many-Core Processors Using On-Chip and Off-Chip Voltage Regulators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Adaptively tolerate power-gating-induced power/ground noise under process variations.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Coherent crosstalk noise analyses in ring-based optical interconnects.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Alleviate chip I/O pin constraints for multicore processors through optical interconnects.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
UNION: A Unified Inter/Intrachip Optical Network for Chip Multiprocessors.
IEEE Trans. Very Large Scale Integr. Syst., 2014

System-Level Modeling and Analysis of Thermal Effects in WDM-Based Optical Networks-on-Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Systematic Analysis of Crosstalk Noise in Folded-Torus-Based Optical Networks-on-Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Floorplan Optimization of Fat-Tree-Based Networks-on-Chip for Chip Multiprocessors.
IEEE Trans. Computers, 2014

SUOR: Sectioned Undirectional Optical Ring for Chip Multiprocessor.
ACM J. Emerg. Technol. Comput. Syst., 2014

On-chip sensor networks for soft-error tolerant real-time multiprocessor systems-on-chip.
ACM J. Emerg. Technol. Comput. Syst., 2014

A Case Study of Signal-to-Noise Ratio in Ring-Based Optical Networks-on-Chip.
IEEE Des. Test, 2014

CLAP: a crosstalk and loss analysis platform for optical interconnects.
Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014

A Case Study on the Communication and Computation Behaviors of Real Applications in NoC-Based MPSoCs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Characterizing power delivery systems with on/off-chip voltage regulators for many-core processors.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

A systematic network-on-chip traffic modeling and generation methodology.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

An extended framework for worst-case throughput analysis with router constraint.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2013
System-Level Modeling and Analysis of Thermal Effects in Optical Networks-on-Chip.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Formal Worst-Case Analysis of Crosstalk Noise in Mesh-Based Optical Networks-on-Chip.
IEEE Trans. Very Large Scale Integr. Syst., 2013

3-D Mesh-Based Optical Network-on-Chip for Multiprocessor System-on-Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Discovery and Design of Tricyclic Scaffolds as Protein Kinase CK2 (CK2) Inhibitors through a Combination of Shape-Based Virtual Screening and Structure-Based Molecular Modification.
J. Chem. Inf. Model., 2013

System-level analysis of mesh-based hybrid optical-electronic network-on-chip.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Active power-gating-induced power/ground noise alleviation using parasitic capacitance of on-chip memories.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
A Torus-Based Hierarchical Optical-Electronic Network-on-Chip for Multiprocessor System-on-Chip.
ACM J. Emerg. Technol. Comput. Syst., 2012

An Novel Effective Simulation Method of Star Atlas for Star Identification.
Proceedings of the Fifth International Joint Conference on Computational Sciences and Optimization, 2012

2011
Satisfiability Modulo Graph Theory for Task Mapping and Scheduling on Multiprocessor Systems.
IEEE Trans. Parallel Distributed Syst., 2011

Coroutine-Based Synthesis of Efficient Embedded Software From SystemC Models.
IEEE Embed. Syst. Lett., 2011

Modeling and Analysis of Thermal Effects in Optical Networks-on-Chip.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

A NoC Traffic Suite Based on Real Applications.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

A Hardware-Software Collaborated Method for Soft-Error Tolerant MPSoC.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

2010
Coverage-hole trap model in target tracking using distributed relay-robot network.
Proceedings of the 2010 ACM Symposium on Applied Computing (SAC), 2010

UNION: A unified inter/intra-chip optical network for chip multiprocessors.
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, 2010

A Hierarchical Hybrid Optical-Electronic Network-on-Chip.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Crosstalk noise and bit error rate analysis for optical network-on-chip.
Proceedings of the 47th Design Automation Conference, 2010

2009
A new framework for on-demand virtualization, repurposing and fusion of heterogeneous sensors.
Proceedings of the 2009 International Symposium on Collaborative Technologies and Systems, 2009

2000
Efficient channel borrowing strategy for real-time services in multimedia wireless networks.
IEEE Trans. Veh. Technol., 2000

1997
Dynamic Slot Allocation Multiple Access Protocol for Wireless ATM Networks.
Proceedings of the 1997 IEEE International Conference on Communications: Towards the Knowledge Millennium, 1997

Clock Recovery for CBR Traffic in Wireless ATM Networks.
Proceedings of the 1997 IEEE International Conference on Communications: Towards the Knowledge Millennium, 1997


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