Xiaowen Jiang

Orcid: 0000-0002-6283-2262

Affiliations:

Zhejiang University, Institute of VLSI Design, Hangzhou, China

According to our database¹, Xiaowen Jiang authored at least 18 papers between 2016 and 2024.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of four.

Timeline

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PhD thesis

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Bibliography

2024

A Response-Feedback-Based Strong PUF with Improved Strict Avalanche Criterion and Reliability.

[BibT_eX]

[DOI]

Sensors, 2024

2023

Structured Dynamic Precision for Deep Neural Networks Quantization.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., January, 2023

Efficient Halftoning via Deep Reinforcement Learning.

[BibT_eX]

[DOI]

IEEE Trans. Image Process., 2023

Structured Term Pruning for Computational Efficient Neural Networks Inference.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023

2022

Acceleration-Aware Fine-Grained Channel Pruning for Deep Neural Networks via Residual Gating.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Flexible and Dynamic Scheduling of Mixed-Criticality Systems.

[BibT_eX]

[DOI]

Sensors, 2022

Structured precision skipping: Accelerating convolutional neural networks with budget-aware dynamic precision selection.

[BibT_eX]

[DOI]

J. Syst. Archit., 2022

Sample-wise dynamic precision quantization for neural network acceleration.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2022

Halftoning with Multi-Agent Deep Reinforcement Learning.

[BibT_eX]

[DOI]

Proceedings of the 2022 IEEE International Conference on Image Processing, 2022

2021

Expected Energy Optimization for Real-Time Multiprocessor SoCs Running Periodic Tasks with Uncertain Execution Time.

[BibT_eX]

[DOI]

IEEE Trans. Sustain. Comput., 2021

2020

IdleSR: Efficient Super-Resolution Network with Multi-scale IdleBlocks.

[BibT_eX]

[DOI]

Proceedings of the Computer Vision - ECCV 2020 Workshops, 2020

2019

A Scalable and Adaptable ILP-Based Approach for Task Mapping on MPSoC Considering Load Balance and Communication Optimization.

[BibT_eX]

[DOI]

Lisane B. de Brisolara

Ahmed Amine Jerraya

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Holistic hardware Trojan design of trigger and payload at gate level with rare switching signals eliminated.

[BibT_eX]

[DOI]

Kai Huang

Yun He

Xiaowen Jiang

IEICE Electron. Express, 2019

Fine-Grained Communication-Aware Task Scheduling Approach for Acyclic and Cyclic Applications on MPSoCs.

[BibT_eX]

[DOI]

IEEE Access, 2019

2018

BFCO: A BPSO-Based Fine-Grained Communication Optimization Method for MPSoC.

[BibT_eX]

[DOI]

IEEE Access, 2018

Energy-Efficient Fault-Tolerant Mapping and Scheduling on Heterogeneous Multiprocessor Real-Time Systems.

[BibT_eX]

[DOI]

IEEE Access, 2018

2017

Providing Predictable Performance via a Slowdown Estimation Model.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2017

2016

Memory Access Scheduling Based on Dynamic Multilevel Priority in Shared DRAM Systems.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2016

Xiaowen Jiang

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