Xiaowen Chen

Orcid: 0000-0003-1865-999X

According to our database1, Xiaowen Chen authored at least 71 papers between 2001 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2024
Spin-Transfer-Torque Magnetic Tunnel Junction Nonlinear In-Sensor Computing Synapse for Improving the Performance of the Feedforward Neural Network.
Adv. Intell. Syst., June, 2024

Analysis of Spatiotemporal Dynamics of Land Desertification in Qilian Mountain National Park Based on Google Earth Engine.
ISPRS Int. J. Geo Inf., April, 2024

Heart rate measurement based on spatiotemporal features of facial key points.
Biomed. Signal Process. Control., 2024

Load balancing-oriented fault-tolerant NoC design.
Proceedings of the IEEE International Test Conference in Asia, 2024

ELSeM: An Efficient and Lightweight Security Mechanism for DSP.
Proceedings of the IEEE International Test Conference in Asia, 2024

2022
Towards Convolutional Neural Network Acceleration and Compression Based on Simonk-Means.
Sensors, 2022

TTQR: A Traffic- and Thermal-Aware Q-Routing for 3D Network-on-Chip.
Sensors, 2022

Discovering sparse control strategies in neural activity.
PLoS Comput. Biol., 2022

Convolutional Neural Network Accelerator for Compression Based on Simon k-means.
Proceedings of the International Joint Conference on Neural Networks, 2022

A Comprehensive Vision-Based Model for Commercial Truck Driver Fatigue Detection.
Proceedings of the Neural Information Processing - 29th International Conference, 2022

HCER: A High Cost-Effectiveness Multi-Bit Fault-Tolerant NoC Router.
Proceedings of the 24th IEEE Int Conf on High Performance Computing & Communications; 8th Int Conf on Data Science & Systems; 20th Int Conf on Smart City; 8th Int Conf on Dependability in Sensor, 2022

2021
Research on Image Retrieval Algorithm Based on Combination of Color and Shape Features.
J. Signal Process. Syst., 2021

Power transformer fault diagnosis system based on Internet of Things.
EURASIP J. Wirel. Commun. Netw., 2021

Systematical identification of cell-specificity of CTCF-gene binding based on epigenetic modifications.
Briefings Bioinform., 2021

Vectorized Winograd's algorithm for Convolution Neural networks.
Proceedings of the 2021 IEEE Intl Conf on Parallel & Distributed Processing with Applications, Big Data & Cloud Computing, Sustainable Computing & Communications, Social Computing & Networking (ISPA/BDCloud/SocialCom/SustainCom), New York City, NY, USA, September 30, 2021

Accelerating Depthwise Separable Convolutions with Vector Processor.
Proceedings of the Artificial Neural Networks and Machine Learning - ICANN 2021, 2021

2020
An Accelerator Design Using a MTCA Decomposition Algorithm for CNNs.
Sensors, 2020

Global Analysis of Gene Expression Profiles Provides Novel Insights into the Development and Evolution of the Large Crustacean <i>Eriocheir sinensis</i>.
Genom. Proteom. Bioinform., 2020

Associative Thread Compaction for Efficient Control Flow Handling in GPGPUs.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

A Research and Design of Lightweight Convolutional Neural Networks Accelerator Based on Systolic Array Structure.
Proceedings of the ICRAI 2020: 6th International Conference on Robotics and Artificial Intelligence, 2020

Middle-School Chinese Students Adjusting to Western Approaches to Teaching and Learning: A Study of Students' Intercultural Competence.
Proceedings of the Interdisciplinarity in the Learning Sciences: Proceedings of the 14th International Conference of the Learning Sciences, 2020

A Design of GEMM Parallel Computing Accelerator Based on Vector SIMD Technology.
Proceedings of the ICCTA 2020: 6th International Conference on Computer and Technology Applications, 2020

2019
Load-Balanced Link Distribution in Mesh-Based Many-Core Systems.
Proceedings of the 21st IEEE International Conference on High Performance Computing and Communications; 17th IEEE International Conference on Smart City; 5th IEEE International Conference on Data Science and Systems, 2019

Efficient Large-Scale 1D FFT Vectorization on Multi-Core Vector Accelerator.
Proceedings of the 21st IEEE International Conference on High Performance Computing and Communications; 17th IEEE International Conference on Smart City; 5th IEEE International Conference on Data Science and Systems, 2019

2018
A Variable-Size FFT Hardware Accelerator Based on Matrix Transposition.
IEEE Trans. Very Large Scale Integr. Syst., 2018

VP-Router: On balancing the traffic load in on-chip networks.
IEICE Electron. Express, 2018

Cache Access Fairness in 3D Mesh-Based NUCA.
IEEE Access, 2018

2017
Round-trip DRAM Access Fairness in 3D NoC-based Many-core Systems.
ACM Trans. Embed. Comput. Syst., 2017

Impact of adjacent transistors on the SEU sensitivity of DICE flip-flop.
IEICE Electron. Express, 2017

A novel power-efficient IC test scheme.
IEICE Electron. Express, 2017

Fairness-oriented switch allocation for networks-on-chip.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

Fairness-Oriented and Location-Aware NUCA for Many-Core SoC.
Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip, 2017

Design and implementation of high-speed configurable ECC co-processor.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016
Iteration Interleaving-Based SIMD Lane Partition.
ACM Trans. Archit. Code Optim., 2016

Multi-bit transient fault control for NoC links using 2D fault coding method.
Proceedings of the Tenth IEEE/ACM International Symposium on Networks-on-Chip, 2016

Dynamic Per-Warp Reconvergence Stack for Efficient Control Flow Handling in GPUs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

2015
Command-Triggered Microcode Execution for Distributed Shared Memory Based Multi-Core Network-on-Chips.
J. Softw., 2015

Performance Analysis of Homogeneous On-Chip Large-Scale Parallel Computing Architectures for Data-Parallel Applications.
J. Electr. Comput. Eng., 2015

Identifying novel associations between small molecules and miRNAs based on integrated molecular networks.
Bioinform., 2015

Achieving Memory Access Equalization Via Round-Trip Routing Latency Prediction in 3D Many-Core NoCs.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

2014
A Coupled Model of the 1D River Network and 3D Estuary Based on Hydrodynamics and Suspended Sediment Simulation.
J. Appl. Math., 2014

Numerical Simulation of Flow and Suspended Sediment Transport in the Distributary Channel Networks.
J. Appl. Math., 2014

Round-trip latency prediction for memory access fairness in mesh-based many-core architectures.
IEICE Electron. Express, 2014

Cooperative communication for efficient and scalable all-to-all barrier synchronization on mesh-based many-core NoCs.
IEICE Electron. Express, 2014

2013
Reducing Virtual-to-Physical address translation overhead in Distributed Shared Memory based multi-core Network-on-Chips according to data property.
Comput. Electr. Eng., 2013

Identification of active transcription factor and miRNA regulatory pathways in Alzheimer's disease.
Bioinform., 2013

2012
CMRF: a Configurable Matrix Register File for accelerating matrix operations on SIMD processors.
IEICE Electron. Express, 2012

Instruction Shuffle: Achieving MIMD-like Performance on SIMD Architectures.
IEEE Comput. Archit. Lett., 2012

Dissection of human MiRNA regulatory influence to subpathway.
Briefings Bioinform., 2012

Multi-scale Segmentation Algorithm Parameters Optimization Based on Evolutionary Computation.
Proceedings of the Computational Intelligence and Intelligent Systems, 2012

Architecture Design Trade-offs among VLIW SIMD and Multi-core Schemes.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

2011
Hybrid Distributed Shared Memory Space in Multi-core Processors.
J. Softw., 2011

Cooperative communication based barrier synchronization in on-chip mesh architectures.
IEICE Electron. Express, 2011

DSBS: Distributed and Scalable Barrier Synchronization in Many-Core Network-on-Chips.
Proceedings of the IEEE 10th International Conference on Trust, 2011

Realization and Scalability of Release and Protected Release Consistency Models in NoC Based Systems.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

Realization and performance comparison of sequential and weak memory consistency models in network-on-chip based multi-core systems.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Design and chip implementation of a heterogeneous multi-core DSP.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010
YHFT-QDSP: High-Performance Heterogeneous Multi-Core DSP.
J. Comput. Sci. Technol., 2010

Handling shared variable synchronization in multi-core Network-on-Chips with distributed memory.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

Multiple Search Centers Based Fast Motion Estimation Algorithm for H.264/AVC.
Proceedings of the 2010 International Conference on Parallel and Distributed Computing, 2010

Run-Time Partitioning of Hybrid Distributed Shared Memory on Multi-core Network-on-Chips.
Proceedings of the Third International Symposium on Parallel Architectures, 2010

Supporting Efficient Synchronization in Multi-core NoCs Using Dynamic Buffer Allocation Technique.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010



Scalability of weak consistency in NoC based multicore architectures.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Mapping of H.264/AVC Encoder on a Hierarchical Chip Multicore DSP Platform.
Proceedings of the 12th IEEE International Conference on High Performance Computing and Communications, 2010

Supporting Distributed Shared Memory on multi-core Network-on-Chips using a dual microcoded controller.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
Scalability of relaxed consistency models in NoC based multicore architectures.
SIGARCH Comput. Archit. News, 2009

2008
Enhanced piecewise regression based on deterministic annealing.
Sci. China Ser. F Inf. Sci., 2008

2007
FCC-SDP: A Fast Close-Coupled Shared Data Pool for Multi-core DSPs.
Proceedings of the Advances in Computer Systems Architecture, 2007

2001
A graphical user interface for executing formal specifications.
Proceedings of the 2001 ACM Symposium on Applied Computing (SAC), 2001


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