Xiaowei Li

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2024

SPFL: A Self-Purified Federated Learning Method Against Poisoning Attacks.

[BibT_eX]

[DOI]

IEEE Trans. Inf. Forensics Secur., 2024

COMET: Towards Partical W4A4KV4 LLMs Serving.

[BibT_eX]

[DOI]

CoRR, 2024

IICPilot: An Intelligent Integrated Circuit Backend Design Framework Using Open EDA.

[BibT_eX]

[DOI]

CoRR, 2024

Graphitron: A Domain Specific Language for FPGA-based Graph Processing Accelerator Generation.

[BibT_eX]

[DOI]

CoRR, 2024

SigDLA: A Deep Learning Accelerator Extension for Signal Processing.

[BibT_eX]

[DOI]

CoRR, 2024

ApproxPilot: A GNN-based Accelerator Approximation Framework.

[BibT_eX]

[DOI]

CoRR, 2024

Efficient Functional Safety Method for Gate-Level Fine-Grained Digital Circuits with ISO-26262.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference in Asia, 2024

A Static Test Compaction Method Based on GCN Assisted Fault Gate Classification.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference in Asia, 2024

AMST: Accelerating Large-Scale Graph Minimum Spanning Tree Computation on FPGA.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2024

Efficient RNIC Cache Side-Channel Attack Detection Through DPU-Driven Architecture.

[BibT_eX]

[DOI]

Proceedings of the Euro-Par 2024: Parallel Processing, 2024

Athena: Add More Intelligence to RMT-Based Network Data Plane with Low-Bit Quantization.

[BibT_eX]

[DOI]

Proceedings of the Euro-Par 2024: Parallel Processing, 2024

A Fully Pipelined High-Performance Elliptic Curve Cryptography Processor for NIST P-256.

[BibT_eX]

[DOI]

Proceedings of the IEEE European Test Symposium, 2024

HyQA: Hybrid Near-Data Processing Platform for Embedding Based Question Answering System.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

Bit-Trimmer: Ineffectual Bit-Operation Removal for CLM Architecture.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

GPACE: An Energy-Efficient PQ-Based GCN Accelerator with Redundancy Reduction.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

Alchemist: A Unified Accelerator Architecture for Cross-Scheme Fully Homomorphic Encryption.

[BibT_eX]

[DOI]

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

Drift: Leveraging Distribution-based Dynamic Precision Quantization for Efficient Deep Neural Network Acceleration.

[BibT_eX]

[DOI]

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

PHD: Parallel Huffman Decoder on FPGA for Extreme Performance and Energy Efficiency.

[BibT_eX]

[DOI]

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

Co-Via: A Video Frame Interpolation Accelerator Exploiting Codec Information Reuse.

[BibT_eX]

[DOI]

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

Chiplever: Towards Effortless Extension of Chiplet-based System for FHE.

[BibT_eX]

[DOI]

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework.

[BibT_eX]

[DOI]

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

TianMen: a DPU-based storage network offloading structure for disaggregated datacenters.

[BibT_eX]

[DOI]

Proceedings of the 2024 ACM Symposium on Cloud Computing, 2024

Chipletizer: Repartitioning SoCs for Cost-Effective Chiplet Integration.

[BibT_eX]

[DOI]

Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

APoX: Accelerate Graph-Based Deep Point Cloud Analysis via Adaptive Graph Construction.

[BibT_eX]

[DOI]

Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

A Fast Test Compaction Method for Commercial DFT Flow Using Dedicated Pure-MaxSAT Solver.

[BibT_eX]

[DOI]

Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

2023

Soft Error Reliability Analysis of Vision Transformers.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., December, 2023

Poseidon-NDP: Practical Fully Homomorphic Encryption Accelerator Based on Near Data Processing Architecture.

[BibT_eX]

[DOI]

Yinghao Yang

Hang Lu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023

Exploring Winograd Convolution for Cost-Effective Neural Network Fault Tolerance.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., November, 2023

Statistical Modeling of Soft Error Influence on Neural Networks.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023

DOE: database offloading engine for accelerating SQL processing.

[BibT_eX]

[DOI]

Distributed Parallel Databases, September, 2023

Accelerating Deformable Convolution Networks with Dynamic and Irregular Memory Accesses.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., July, 2023

Scalable and Conflict-Free NTT Hardware Accelerator Design: Methodology, Proof, and Implementation.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., May, 2023

On-Line Fault Protection for ReRAM-Based Neural Networks.

[BibT_eX]

[DOI]

IEEE Trans. Computers, February, 2023

BitXpro: Regularity-Aware Hardware Runtime Pruning for Deep Neural Networks.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2023

DHSA: efficient doubly homomorphic secure aggregation for cross-silo federated learning.

[BibT_eX]

[DOI]

J. Supercomput., 2023

Chosen ciphertext correlation power analysis on Kyber.

[BibT_eX]

[DOI]

Integr., 2023

Cross-Layer Optimization for Fault-Tolerant Deep Learning.

[BibT_eX]

[DOI]

CoRR, 2023

MRFI: An Open Source Multi-Resolution Fault Injection Framework for Neural Network Processing.

[BibT_eX]

[DOI]

CoRR, 2023

ChipGPT: How far are we from natural language hardware design.

[BibT_eX]

[DOI]

CoRR, 2023

ApproxABFT: Approximate Algorithm-Based Fault Tolerance for Vision Transformers.

[BibT_eX]

[DOI]

CoRR, 2023

Reliability Analysis of Vision Transformers.

[BibT_eX]

[DOI]

CoRR, 2023

BitColor: Accelerating Large-Scale Graph Coloring on FPGA with Parallel Bit-Wise Engines.

[BibT_eX]

[DOI]

Proceedings of the 52nd International Conference on Parallel Processing, 2023

PANG: A Pattern-Aware GCN Accelerator for Universal Graphs.

[BibT_eX]

[DOI]

Proceedings of the 41st IEEE International Conference on Computer Design, 2023

DeepBurning-MixQ: An Open Source Mixed-Precision Neural Network Accelerator Design Framework for FPGAs.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Poseidon: Practical Homomorphic Encryption Accelerator.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023

Optimize the TX Architecture of RDMA NIC for Performance Isolation in the Cloud Environment.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

KPU-SQL: Kernel Processing Unit for High-Performance SQL Acceleration.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

M2VT: A Multi-Output Encoder Accelerator for Multiple-Way Video Transcoding.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

Co-ViSu: a Video Super-Resolution Accelerator Exploiting Codec Information Reuse.

[BibT_eX]

[DOI]

Proceedings of the 33rd International Conference on Field-Programmable Logic and Applications, 2023

Online Reliability Evaluation Design: Select Reliable CRPs for Arbiter PUF and Its Variants.

[BibT_eX]

[DOI]

Proceedings of the IEEE European Test Symposium, 2023

Energy-efficient NTT Design with One-bank SRAM and 2-D PE Array.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

A Template Attack on Reduction Without Reference Device on Kyber.

[BibT_eX]

[DOI]

Proceedings of the 32nd IEEE Asian Test Symposium, 2023

Configurable and High-Level Pipelined Lattice-Based Post Quantum Cryptography Hardware Accelerator Design.

[BibT_eX]

[DOI]

Proceedings of the 32nd IEEE Asian Test Symposium, 2023

Adversarial Testing: A Novel On-Line Testing Method for Deep Learning Processors.

[BibT_eX]

[DOI]

Proceedings of the 32nd IEEE Asian Test Symposium, 2023

A Distributed ATPG System Combining Test Compaction Based on Pure MaxSAT.

[BibT_eX]

[DOI]

Proceedings of the 32nd IEEE Asian Test Symposium, 2023

Built-in Fault-Tolerant Computing Paradigm for Resilient Large-Scale Chip Design - A Self-Test, Self-Diagnosis, and Self-Repair-Based Approach

[BibT_eX]

[DOI]

Cheng Liu

Springer, ISBN: 978-981-19-8550-8, 2023

2022

Taming Process Variations in CNFET for Efficient Last-Level Cache Design.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2022

An Efficient Deep Learning Accelerator Architecture for Compressed Video Analysis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

A Fast Precision Tuning Solution for Always-On DNN Accelerators.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

HyCA: A Hybrid Computing Architecture for Fault-Tolerant Deep Learning.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Saving Energy of RRAM-Based Neural Accelerator Through State-Aware Computing.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

CAP: Communication-Aware Automated Parallelization for Deep Learning Inference on CMP Architectures.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2022

Portrait: A holistic computation and bandwidth balanced performance evaluation model for heterogeneous systems.

[BibT_eX]

[DOI]

Sustain. Comput. Informatics Syst., 2022

A robust authentication scheme for remote diagnosis and maintenance in 5G V2N.

[BibT_eX]

[DOI]

J. Netw. Comput. Appl., 2022

STC-NAS: Fast neural architecture search with source-target consistency.

[BibT_eX]

[DOI]

Neurocomputing, 2022

Fault-Tolerant Deep Learning: A Hierarchical Perspective.

[BibT_eX]

[DOI]

CoRR, 2022

VNet: a versatile network to train real-time semantic segmentation models on a single GPU.

[BibT_eX]

[DOI]

Sci. China Inf. Sci., 2022

Cognitive SSD+: a deep learning engine for energy-efficient unstructured data retrieval.

[BibT_eX]

[DOI]

CCF Trans. High Perform. Comput., 2022

Special Session: Fault-Tolerant Deep Learning: A Hierarchical Perspective.

[BibT_eX]

[DOI]

Proceedings of the 40th IEEE VLSI Test Symposium, 2022

SASH: Efficient secure aggregation based on SHPRG for federated learning.

[BibT_eX]

[DOI]

Proceedings of the Uncertainty in Artificial Intelligence, 2022

Exploring the high-throughput and low-delay hardware design of SM4 on FPGA.

[BibT_eX]

[DOI]

Proceedings of the 19th International SoC Design Conference, 2022

Closing the Dynamics Gap via Adversarial and Reinforcement Learning for High-Speed Racing.

[BibT_eX]

[DOI]

Proceedings of the International Joint Conference on Neural Networks, 2022

Searching for BurgerFormer with Micro-Meso-Macro Space Design.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Machine Learning, 2022

AGNAS: Attention-Guided Micro and Macro-Architecture Search.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Machine Learning, 2022

DOE: Database Offloading Engine for Accelerating SQL Processing.

[BibT_eX]

[DOI]

Proceedings of the 38th IEEE International Conference on Data Engineering Workshops, 2022

Reexamining CGRA Memory Sub-system for Higher Memory Utilization and Performance.

[BibT_eX]

[DOI]

Proceedings of the IEEE 40th International Conference on Computer Design, 2022

GIA: A Reusable General Interposer Architecture for Agile Chiplet Integration.

[BibT_eX]

[DOI]

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

NoCeption: A Fast PPA Prediction Framework for Network-on-Chips Using Graph Neural Network.

[BibT_eX]

[DOI]

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

VStore: in-storage graph based vector search accelerator.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

InfoX: an energy-efficient ReRAM accelerator design with information-lossless low-bit ADCs.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

A Voltage Template Attack on the Modular Polynomial Subtraction in Kyber.

[BibT_eX]

[DOI]

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021

R2F: A Remote Retraining Framework for AIoT Processors With Computing Errors.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2021

An Edge 3D CNN Accelerator for Low-Power Activity Recognition.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Chaotic Weights: A Novel Approach to Protect Intellectual Property of Deep Neural Networks.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

EnGN: A High-Throughput and Energy-Efficient Accelerator for Large Graph Neural Networks.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2021

ShuntFlowPlus: An Efficient and Scalable Dataflow Accelerator Architecture for Stream Applications.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2021

Efficient Secure Aggregation Based on SHPRG For Federated Learning.

[BibT_eX]

[DOI]

CoRR, 2021

Taming Process Variations in CNFET for Efficient Last Level Cache Design.

[BibT_eX]

[DOI]

CoRR, 2021

Energy-Efficient Accelerator Design for Deformable Convolution Networks.

[BibT_eX]

[DOI]

CoRR, 2021

Internet connected vehicle platoon system modeling and linear stability analysis.

[BibT_eX]

[DOI]

Comput. Commun., 2021

To cloud or not to cloud: an on-line scheduler for dynamic privacy-protection of deep learning workload on edge devices.

[BibT_eX]

[DOI]

CCF Trans. High Perform. Comput., 2021

Happy Emotion Recognition From Unconstrained Videos Using 3D Hybrid Deep Features.

[BibT_eX]

[DOI]

IEEE Access, 2021

Special Session - Test for AI Chips: from DFT to On-line Testing.

[BibT_eX]

[DOI]

Proceedings of the 39th IEEE VLSI Test Symposium, 2021

GLIST: Towards In-Storage Graph Learning.

[BibT_eX]

[DOI]

Proceedings of the 2021 USENIX Annual Technical Conference, 2021

KFS-LIO: Key-Feature Selection for Lightweight Lidar Inertial Odometry.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Robotics and Automation, 2021

BitX: Empower Versatile Inference with Hardware Runtime Pruning.

[BibT_eX]

[DOI]

Proceedings of the ICPP 2021: 50th International Conference on Parallel Processing, Lemont, IL, USA, August 9, 2021

PixelSieve: Towards Efficient Activity Analysis From Compressed Video Streams.

[BibT_eX]

[DOI]

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

TARe: Task-Adaptive in-situ ReRAM Computing for Graph Learning.

[BibT_eX]

[DOI]

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

GCiM: A Near-Data Processing Accelerator for Graph Construction.

[BibT_eX]

[DOI]

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

DU-DARTS: Decreasing the Uncertainty of Differentiable Architecture Search.

[BibT_eX]

[DOI]

Proceedings of the 32nd British Machine Vision Conference 2021, 2021

SeGa: A Trojan Detection Method Combined With Gate Semantics.

[BibT_eX]

[DOI]

Proceedings of the 30th IEEE Asian Test Symposium, 2021

ChaoPIM: A PIM-based Protection Framework for DNN Accelerators Using Chaotic Encryption.

[BibT_eX]

[DOI]

Proceedings of the 30th IEEE Asian Test Symposium, 2021

DDSAS: Dynamic and Differentiable Space-Architecture Search.

[BibT_eX]

[DOI]

Proceedings of the Asian Conference on Machine Learning, 2021

2020

Architecting Effectual Computation for Machine Learning Accelerators.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

BZIP: A compact data memory system for UTXO-based blockchains.

[BibT_eX]

[DOI]

J. Syst. Archit., 2020

Evaluating and Constraining Hardware Assertions with Absent Scenarios.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2020

INOR - An Intelligent noise reduction method to defend against adversarial audio examples.

[BibT_eX]

[DOI]

Neurocomputing, 2020

Trajectory Tracking Based on Adaptive Sliding Mode Control for Agricultural Tractor.

[BibT_eX]

[DOI]

IEEE Access, 2020

MultiPAD: A Multivariant Partition-Based Method for Audio Adversarial Examples Detection.

[BibT_eX]

[DOI]

IEEE Access, 2020

Sequence Triggered Hardware Trojan in Neural Network Accelerator.

[BibT_eX]

[DOI]

Proceedings of the 38th IEEE VLSI Test Symposium, 2020

Two-Stage Safe Reinforcement Learning for High-Speed Autonomous Racing.

[BibT_eX]

[DOI]

Proceedings of the 2020 IEEE International Conference on Systems, Man, and Cybernetics, 2020

A Many-Core Accelerator Design for On-Chip Deep Reinforcement Learning.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

DeepBurning-GL: an Automated Framework for Generating Graph Neural Network Accelerators.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Prediction Stability: A New Metric for Quantitatively Evaluating DNN Outputs.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

An Efficient Deep Learning Accelerator for Compressed Video Analysis.

[BibT_eX]

[DOI]

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

Towards State-Aware Computation in ReRAM Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

Exploring Spatial-Temporal Multi-Frequency Analysis for High-Fidelity and Temporal-Consistency Video Prediction.

[BibT_eX]

[DOI]

Proceedings of the 2020 IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2020

Optimization Space Exploration of Hardware Design for CRYSTALS-KYBER.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE Asian Test Symposium, 2020

Survey: Hardware Trojan Detection for Netlist.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE Asian Test Symposium, 2020

Search-free Accelerator for Sparse Convolutional Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019

SynergyFlow: An Elastic Accelerator Architecture Supporting Batch Processing of Large-Scale Deep Neural Networks.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2019

Comments on "Provably Secure Dynamic Id-Based Anonymous Two-Factor Authenticated Key Exchange Protocol With Extended Security Model".

[BibT_eX]

[DOI]

IEEE Trans. Inf. Forensics Secur., 2019

ShuttleNoC: Power-Adaptable Communication Infrastructure for Many-Core Processors.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Cluster Restoration-Based Trace Signal Selection for Post-Silicon Debug.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

A QoS-QoR Aware CNN Accelerator Design Approach.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Promoting the Harmony between Sparsity and Regularity: A Relaxed Synchronous Architecture for Convolutional Neural Networks.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2019

SqueezeFlow: A Sparse CNN Accelerator Exploiting Concise Convolution Rules.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2019

MV-Net: Toward Real-Time Deep Learning on Mobile GPGPU Systems.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2019

PUFPass: A password management mechanism based on software/hardware codesign.

[BibT_eX]

[DOI]

Integr., 2019

Thread: Towards fine-grained precision reconfiguration in variable-precision neural network accelerator.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2019

HTDet: A Clustering Method using Information Entropy for Hardware Trojan Detection.

[BibT_eX]

[DOI]

CoRR, 2019

Accelerating DNN-based 3D point cloud processing for mobile computing.

[BibT_eX]

[DOI]

Sci. China Inf. Sci., 2019

PIMSim: A Flexible and Detailed Processing-in-Memory Simulator.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2019

Scan Chain Based Attacks and Countermeasures: A Survey.

[BibT_eX]

[DOI]

IEEE Access, 2019

Leveraging Memory PUFs and PIM-based encryption to secure edge deep learning systems.

[BibT_eX]

[DOI]

Proceedings of the 37th IEEE VLSI Test Symposium, 2019

Cognitive SSD: A Deep Learning Engine for In-Storage Data Retrieval.

[BibT_eX]

[DOI]

Proceedings of the 2019 USENIX Annual Technical Conference, 2019

China Test Conference (CTC) - Extending the Global Test Forum to China.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2019

Asian Test Symposium - Past, Present and Future -.

[BibT_eX]

[DOI]

Michiko Inoue

Cheng-Wen Wu

Proceedings of the IEEE International Test Conference, 2019

Implementation of Parametric Hardware Trojan in FPGA.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference in Asia, 2019

Squeezing the Last MHz for CNN Acceleration on FPGAs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference in Asia, 2019

Instruction Vulnerability Test and Code Optimization Against DVFS Attack.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference in Asia, 2019

iATPG: Instruction-level Automatic Test Program Generation for Vulnerabilities under DVFS attack.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

When Deep Learning Meets the Edge: Auto-Masking Deep Neural Networks for Efficient Machine Learning on Edge Devices.

[BibT_eX]

[DOI]

Proceedings of the 37th IEEE International Conference on Computer Design, 2019

VNet: A Versatile Network for Efficient Real-Time Semantic Segmentation.

[BibT_eX]

[DOI]

Proceedings of the 37th IEEE International Conference on Computer Design, 2019

RRAMedy: Protecting ReRAM-Based Neural Network from Permanent and Soft Faults During Its Lifetime.

[BibT_eX]

[DOI]

Proceedings of the 37th IEEE International Conference on Computer Design, 2019

An Agile Precision-Tunable CNN Accelerator based on ReRAM.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2019

MLA: Machine Learning Adaptation for Realtime Streaming Financial Applications.

[BibT_eX]

[DOI]

Proceedings of the Tenth International Green and Sustainable Computing Conference, 2019

InS-DLA: An In-SSD Deep Learning Accelerator for Near-Data Processing.

[BibT_eX]

[DOI]

Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

Learn-to-Scale: Parallelizing Deep Learning Inference on Chip Multiprocessor Architecture.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Systolic Cube: A Spatial 3D CNN Accelerator Architecture for Low Power Video Analysis.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

A None-Sparse Inference Accelerator that Distills and Reuses the Computation Redundancy in CNNs.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

HeadStart: Enforcing Optimal Inceptions in Pruning Deep Neural Networks for Efficient Inference on GPGPUs.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

ShuntFlow: An Efficient and Scalable Dataflow Accelerator Architecture for Streaming Applications.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

GramsDet: Hardware Trojan Detection Based on Recurrent Neural Network.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE Asian Test Symposium, 2019

CuckooPIM: an efficient and less-blocking coherence mechanism for processing-in-memory systems.

[BibT_eX]

[DOI]

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

Addressing the issue of processing element under-utilization in general-purpose systolic deep learning accelerators.

[BibT_eX]

[DOI]

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

Redeeming chip-level power efficiency by collaborative management of the computation and communication.

[BibT_eX]

[DOI]

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

TNPU: an efficient accelerator architecture for training convolutional neural networks.

[BibT_eX]

[DOI]

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

P<sup>3</sup>M: a PIM-based neural network model protection scheme for deep learning accelerator.

[BibT_eX]

[DOI]

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

Simulate-the-hardware: training accurate binarized neural networks for low-precision neural accelerators.

[BibT_eX]

[DOI]

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018

LMDet: A "Naturalness" Statistical Method for Hardware Trojan Detection.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2018

Deterministic and Probabilistic Diagnostic Challenge Generation for Arbiter Physical Unclonable Function.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

A Case of On-Chip Memory Subsystem Design for Low-Power CNN Accelerators.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

A Low Overhead In-Network Data Compressor for the Memory Hierarchy of Chip Multiprocessors.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

On Trace Buffer Reuse-Based Trigger Generation in Post-Silicon Debug.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

RT3D: Real-Time 3-D Vehicle Detection in LiDAR Point Cloud for Autonomous Driving.

[BibT_eX]

[DOI]

IEEE Robotics Autom. Lett., 2018

AdaFlow: Aggressive Convolutional Neural Networks Approximation by Leveraging the Input Variability.

[BibT_eX]

[DOI]

Wenyan Lu

J. Low Power Electron., 2018

Optimizing Memory Efficiency for Deep Convolutional Neural Network Accelerators.

[BibT_eX]

[DOI]

Jiajun Li

J. Low Power Electron., 2018

Fault tolerance on-chip: a reliable computing paradigm using self-test, self-diagnosis, and self-repair (3S) approach.

[BibT_eX]

[DOI]

Sci. China Inf. Sci., 2018

Modeling attacks on strong physical unclonable functions strengthened by random number and weak PUF.

[BibT_eX]

[DOI]

Proceedings of the 36th IEEE VLSI Test Symposium, 2018

See and Think: Disentangling Semantic Scene Completion.

[BibT_eX]

[DOI]

Proceedings of the Advances in Neural Information Processing Systems 31: Annual Conference on Neural Information Processing Systems 2018, 2018

Lightweight Timing Channel Protection for Shared DRAM Controller.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2018

Grey Zone in Pre-Silicon Hardware Trojan Detection.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference in Asia, 2018

Leveraging DRAM Refresh to Protect the Memory Timing Channel of Cloud Chip Multi-processors.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference in Asia, 2018

Tetris: re-architecting convolutional neural network computation for machine learning accelerators.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2018

A retrospective evaluation of energy-efficient object detection solutions on embedded devices.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

SmartShuttle: Optimizing off-chip memory accesses for deep learning accelerators.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

CCR: A concise convolution rule for sparse neural network accelerators.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Hardware Trojan Detection Based on Signal Correlation.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE Asian Test Symposium, 2018

Hardware Trojan in FPGA CNN Accelerator.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE Asian Test Symposium, 2018

RiskCap: Minimizing Effort of Error Regulation for Approximate Computing.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE Asian Test Symposium, 2018

PUF Based Pay-Per-Device Scheme for IP Protection of CNN Model.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE Asian Test Symposium, 2018

XORiM: A case of in-memory bit-comparator implementation and its performance implications.

[BibT_eX]

[DOI]

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

PIMCH: Cooperative memory prefetching in processing-in-memory architecture.

[BibT_eX]

[DOI]

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

Bias PUF based Secure Scan Chain Design.

[BibT_eX]

[DOI]

Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2018

2017

Resilience-Aware Frequency Tuning for Neural-Network-Based Approximate Computing Chips.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

STT-RAM Buffer Design for Precision-Tunable General-Purpose Neural Network Accelerator.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

Going Cooler With Timing-Constrained TeSHoP: A Temperature Sensing-Based Hotspot-Driven Placement Technique for FPGAs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

PowerTrader: Enforcing Autonomous Power Management for Future Large-Scale Many-Core Processors.

[BibT_eX]

[DOI]

IEEE Trans. Multi Scale Comput. Syst., 2017

Exploiting the Potential of Computation Reuse Through Approximate Computing.

[BibT_eX]

[DOI]

IEEE Trans. Multi Scale Comput. Syst., 2017

Retention-Aware DRAM Assembly and Repair for Future FGR Memories.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Power-Utility-Driven Write Management for MLC PCM.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2017

LAPS: Layout-Aware Path Selection for Post-Silicon Timing Characterization.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2017

Innovative practices session 10C formal verification practices in industry.

[BibT_eX]

[DOI]

Proceedings of the 35th IEEE VLSI Test Symposium, 2017

Flip-flop clustering based trace signal selection for post-silicon debug.

[BibT_eX]

[DOI]

Proceedings of the 35th IEEE VLSI Test Symposium, 2017

GeoCueDepth: Exploiting geometric structure cues to estimate depth from a single image.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE/RSJ International Conference on Intelligent Robots and Systems, 2017

VPUF: Voter based physical unclonable function with high reliability and modeling attack resistance.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

Polymorphic PUF: Exploiting reconfigurability of CPU+FPGA SoC to resist modeling attack.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

FlexFlow: A Flexible Dataflow Accelerator Architecture for Convolutional Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

Leveraging FVT-margins in design space exploration for FFGA-based CNN accelerators.

[BibT_eX]

[DOI]

Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

Fault diagnosis of arbiter physical unclonable function.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Real-Time Meets Approximate Computing: An Elastic CNN Inference Accelerator with Adaptive Trade-off between QoS and QoR.

[BibT_eX]

[DOI]

Proceedings of the 54th Annual Design Automation Conference, 2017

Dadu: Accelerating Inverse Kinematics for High-DOF Robots.

[BibT_eX]

[DOI]

Proceedings of the 54th Annual Design Automation Conference, 2017

Selective off-loading to Memory: Task Partitioning and Mapping for PIM-enabled Heterogeneous Systems.

[BibT_eX]

[DOI]

Proceedings of the Computing Frontiers Conference, 2017

On Evaluating and Constraining Assertions Using Conflicts in Absent Scenarios.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE Asian Test Symposium, 2017

CNN-based object detection solutions for embedded heterogeneous multicore SoCs.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

ApproxPIM: Exploiting realistic 3D-stacked DRAM for energy-efficient processing in-memory.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

BoDNoC: Providing bandwidth-on-demand interconnection for multi-granularity memory systems.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

ApproxEye: Enabling approximate computation reuse for microrobotic computer vision.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016

PSI Conscious Write Scheduling: Architectural Support for Reliable Power Delivery in 3-D Die-Stacked PCM.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

VANUCA: Enabling Near-Threshold Voltage Operation in Large-Capacity Cache.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

Enhanced Wear-Rate Leveling for PRAM Lifetime Improvement Considering Process Variation.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

EcoUp: Towards Economical Datacenter Upgrading.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2016

Functional Test Generation for Hard-to-Reach States Using Path Constraint Solving.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Abstraction-Guided Simulation Using Markov Analysis for Functional Verification.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

CoreRank: Redeeming "Sick Silicon" by Dynamically Quantifying Core-Level Healthy Condition.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2016

An Analytical Framework for Estimating Scale-Out and Scale-Up Power Efficiency of Heterogeneous Manycores.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2016

Wide Operational Range Processor Power Delivery Design for Both Super-Threshold Voltage and Near-Threshold Voltage Computing.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2016

One-round Secure Key Exchange Protocol With Strong Forward Secrecy.

[BibT_eX]

[DOI]

KSII Trans. Internet Inf. Syst., 2016

LOFT: A low-overhead fault-tolerant routing scheme for 3D NoCs.

[BibT_eX]

[DOI]

Integr., 2016

Path constraint solving based test generation for observability-enhanced branch coverage.

[BibT_eX]

[DOI]

Proceedings of the 34th IEEE VLSI Test Symposium, 2016

An accurate algorithm for computing mutation coverage in model checking.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Test Conference, 2016

Re-architecting the on-chip memory sub-system of machine-learning accelerator for embedded devices.

[BibT_eX]

[DOI]

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

RPUF: Physical Unclonable Function with Randomized Challenge to resist modeling attack.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE Asian Hardware-Oriented Security and Trust, 2016

TeSHoP: A Temperature Sensing based Hotspot-Driven Placement technique for FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

DCPUF: Placement and Routing Constraint based Dynamically Configured Physical Unclonable Function on FPGA (Abstact Only).

[BibT_eX]

[DOI]

Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

Frequency scheduling for resilient chip multi-processors operating at Near Threshold Voltage.

[BibT_eX]

[DOI]

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

DeepBurning: automatic generation of FPGA-based learning accelerators for the neural network family.

[BibT_eX]

[DOI]

Proceedings of the 53rd Annual Design Automation Conference, 2016

DISCO: a low overhead in-network data compressor for energy-efficient chip multi-processors.

[BibT_eX]

[DOI]

Proceedings of the 53rd Annual Design Automation Conference, 2016

C-brain: a deep learning accelerator that tames the diversity of CNNs through adaptive data-level parallelization.

[BibT_eX]

[DOI]

Proceedings of the 53rd Annual Design Automation Conference, 2016

POSTER: Attack on Non-Linear Physical Unclonable Function.

[BibT_eX]

[DOI]

Proceedings of the 2016 ACM SIGSAC Conference on Computer and Communications Security, 2016

Property Coverage Analysis Based Trustworthiness Verification for Potential Threats from EDA Tools.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE Asian Test Symposium, 2016

Efficient Attack on Non-linear Current Mirror PUF with Genetic Algorithm.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE Asian Test Symposium, 2016

ACR: Enabling computation reuse for approximate computing.

[BibT_eX]

[DOI]

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015

Diagnosis and Layout Aware (DLA) Scan Chain Stitching.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

Data Remapping for Static NUCA in Degradable Chip Multiprocessors.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

Economizing TSV Resources in 3-D Network-on-Chip Design.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

RISO: Enforce Noninterfered Performance With Relaxed Network-on-Chip Isolation in Many-Core Cloud Processors.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

A privacy preserving authentication scheme for roaming services in global mobility networks.

[BibT_eX]

[DOI]

Secur. Commun. Networks, 2015

An on-chip frequency programmable test clock generation and application method for small delay defect detection.

[BibT_eX]

[DOI]

Integr., 2015

A signal degradation reduction method for memristor ratioed logic (MRL) gates.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2015

A Similarity Based Circuit Partitioning and Trimming Method to Defend against Hardware Trojans.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

A case of precision-tunable STT-RAM memory design for approximate neural network.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

OPUF: Obfuscation logic based physical unclonable function.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015

Retraining-based timing error mitigation for hardware neural networks.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

<i>RADAR</i>: a case for retention-aware DRAM assembly and repair in future FGR DRAM memory.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual Design Automation Conference, 2015

ProPRAM: exploiting the transparent logic resources in non-volatile memory for near data computing.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual Design Automation Conference, 2015

Impact assessment of net metering on smart home cyberattack detection.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual Design Automation Conference, 2015

TURO: A lightweight turn-guided routing scheme for 3D NoCs.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE Symposium in Low-Power and High-Speed Chips, 2015

TWiN: A Turn-Guided Reliable Routing Scheme for Wireless 3D NoCs.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE Asian Test Symposium, 2015

A Lightweight Timing Channel Protection for Shared Memory Controllers.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE Asian Test Symposium, 2015

ShuttleNoC: Boosting on-chip communication efficiency by enabling localized power adaptation.

[BibT_eX]

[DOI]

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014

Diagnose Failures Caused by Multiple Locations at a Time.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

Test-Quality Optimization for Variable $n$ -Detections of Transition Faults.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

Reliability-Oriented Placement and Routing Algorithm for SRAM-Based FPGAs.

[BibT_eX]

[DOI]

Keheng Huang

IEEE Trans. Very Large Scale Integr. Syst., 2014

Orchestrator: Guarding Against Voltage Emergencies in Multithreaded Applications.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

ZoneDefense: A Fault-Tolerant Routing for 2-D Meshes Without Virtual Channels.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

Lifetime Enhancement Techniques for PCM-Based Image Buffer in Multimedia Applications.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

SmartCap: Using Machine Learning for Power Adaptation of Smartphone's Application Processor.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2014

A novel abstraction-guided simulation approach using posterior probabilities for verification.

[BibT_eX]

[DOI]

Jian Wang

Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

Short-SET: An energy-efficient write scheme for MLC PCM.

[BibT_eX]

[DOI]

Bing Li

Proceedings of the IEEE Non-Volatile Memory Systems and Applications Symposium, 2014

HARS: A High-Performance Reliable Routing Scheme for 3D NoCs.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Data-aware DRAM refresh to squeeze the margin of retention time in hybrid memory cube.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Functional test generation guided by steady-state probabilities of abstract design.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Partial-SET: Write speedup of PCM main memory.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

SuperRange: Wide operational range power delivery design for both STV and NTV computing.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

On-Chip Delay Sensor for Environments with Large Temperature Fluctuations.

[BibT_eX]

[DOI]

Jibing Qiu

Proceedings of the 23rd IEEE Asian Test Symposium, 2014

An On-Line Timing Error Detection Method for Silicon Debug.

[BibT_eX]

[DOI]

Yun Cheng

Proceedings of the 23rd IEEE Asian Test Symposium, 2014

Amphisbaena: Modeling two orthogonal ways to hunt on heterogeneous many-cores.

[BibT_eX]

[DOI]

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013

Automatic Test Program Generation Using Executing-Trace-Based Constraint Extraction for Embedded Processors.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

Unified Capture Scheme for Small Delay Defect Detection and Aging Prediction.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

Test Path Selection for Capturing Delay Failures Under Statistical Timing Model.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

Thermal-Constrained Task Allocation for Interconnect Energy Reduction in 3-D Homogeneous MPSoCs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

A new certificateless authenticated key agreement protocol for SIP with different KGCs.

[BibT_eX]

[DOI]

Yuqing Zhang

Geifei Zhang

Secur. Commun. Networks, 2013

A simple and robust anonymous two-factor authenticated key exchange protocol.

[BibT_eX]

[DOI]

Yuqing Zhang

Secur. Commun. Networks, 2013

RevivePath: Resilient Network-on-Chip Design Through Data Path Salvaging of Router.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2013

TSV Minimization for Circuit - Partitioned 3D SoC Test Wrapper Design.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2013

A New Roaming Authentication Framework For Wireless Communication.

[BibT_eX]

[DOI]

KSII Trans. Internet Inf. Syst., 2013

A Lightweight Three-Party Privacy-preserving Authentication Key Exchange Protocol Using Smart Card.

[BibT_eX]

[DOI]

KSII Trans. Internet Inf. Syst., 2013

RSAK: Random stream attack for phase change memory in video applications.

[BibT_eX]

[DOI]

Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Tolerating Noise in MLC PCM with Multi-Bit Error Correction Code.

[BibT_eX]

[DOI]

Proceedings of the IEEE 19th Pacific Rim International Symposium on Dependable Computing, 2013

On predicting NBTI-induced circuit aging by isolating leakage change.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Quality Electronic Design, 2013

Enabling Near-Threshold Voltage(NTV) operation in Multi-VDD cache for power reduction.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

HHC: Hierarchical hardware checkpointing to accelerate fault recovery for SRAM-based FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

Capturing post-silicon variation by layout-aware path-delay testing.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

SmartCap: user experience-oriented power adaptation for smartphone's application processor.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

Orchestrator: a low-cost solution to reduce voltage emergencies for multi-threaded applications.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

RISO: relaxed network-on-chip isolation for cloud processors.

[BibT_eX]

[DOI]

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Path Constraint Solving Based Test Generation for Hard-to-Reach States.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asian Test Symposium, 2013

2012

An energy-efficient link quality monitoring scheme for wireless networks.

[BibT_eX]

[DOI]

Wirel. Commun. Mob. Comput., 2012

Flip-Flop Selection for Partial Enhanced Scan to Reduce Transition Test Data Volume.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2012

A High-Precision On-Chip Path Delay Measurement Architecture.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2012

IVF: Characterizing the Vulnerability of Microprocessor Structures to Intermittent Faults.

[BibT_eX]

[DOI]

Songjun Pan

IEEE Trans. Very Large Scale Integr. Syst., 2012

Testable Path Selection and Grouping for Faster Than At-Speed Testing.

[BibT_eX]

[DOI]

Xiang Fu

IEEE Trans. Very Large Scale Integr. Syst., 2012

Statistical SDFC: A metric for evaluating test quality of small delay faults.

[BibT_eX]

[DOI]

Xuefeng Zhu

Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

AgileRegulator: A hybrid voltage regulator scheme redeeming dark silicon for power efficiency in a multicore architecture.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012

A lightweight roaming authentication protocol for anonymous wireless communication.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE Global Communications Conference, 2012

Off-path leakage power aware routing for SRAM-based FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

A clustering-based scheme for concurrent trace in debugging NoC-based multicore systems.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

In-Field Testing of NAND Flash Storage: Why and How?

[BibT_eX]

[DOI]

Xinli Gu

Proceedings of the 21st IEEE Asian Test Symposium, 2012

SoftPCM: Enhancing Energy Efficiency and Lifetime of Phase Change Memory in Video Applications via Approximate Write.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE Asian Test Symposium, 2012

Hungarian algorithm based virtualization to maintain application timing similarity for defect-tolerant NoC.

[BibT_eX]

[DOI]

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011

Selected Transition Time Adjustment for Tolerating Crosstalk Effects on Network-on-Chip Interconnects.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2011

Path Delay Test Generation Toward Activation of Worst Case Coupling Effects.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2011

SVFD: A Versatile Online Fault Detection Scheme via Checking of Stability Violation.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2011

MicroFix: Using timing interpolation and delay sensors for power reduction.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2011

A Loss Inference Algorithm for Wireless Sensor Networks to Improve Data Reliability of Digital Ecosystems.

[BibT_eX]

[DOI]

IEEE Trans. Ind. Electron., 2011

Nonidentical Linear Pulse-Coupled Oscillators Model With Application to Time Synchronization in Wireless Sensor Networks.

[BibT_eX]

[DOI]

IEEE Trans. Ind. Electron., 2011

ReviveNet: A Self-Adaptive Architecture for Improving Lifetime Reliability via Localized Timing Adaptation.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2011

New Methodologies for Parallel Architecture.

[BibT_eX]

[DOI]

Dong-Rui Fan

Guo-Jie Li

J. Comput. Sci. Technol., 2011

Capture-power-aware test data compression using selective encoding.

[BibT_eX]

[DOI]

Integr., 2011

Statistical lifetime reliability optimization considering joint effect of process variation and aging.

[BibT_eX]

[DOI]

Integr., 2011

A New Multiple-Round Dimension-Order Routing for Networks-on-Chip.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2011

A Security Mechanism For RFID With Dependable Proxy.

[BibT_eX]

[DOI]

Jun Zhou

Yongjun Xu

Intell. Autom. Soft Comput., 2011

Oware: Operand width Aware Redundant Execution for Whole-Processor Error Detection.

[BibT_eX]

[DOI]

Zhongliang Chen

Intell. Autom. Soft Comput., 2011

Scan chain design for shift power reduction in scan-based testing.

[BibT_eX]

[DOI]

Jia Li

Sci. China Inf. Sci., 2011

A unified test architecture for on-line and off-line delay fault detections.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE VLSI Test Symposium, 2011

Online timing variation tolerance for digital integrated circuits.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Test Conference, 2011

An abacus turn model for time/space-efficient reconfigurable routing.

[BibT_eX]

[DOI]

Proceedings of the 38th International Symposium on Computer Architecture (ISCA 2011), 2011

A greedy approach to tolerate defect cores for multimedia applications.

[BibT_eX]

[DOI]

Proceedings of the 9th IEEE Symposium on Embedded Systems for Real-Time Multimedia, 2011

Transparent dynamic binding with fault-tolerant cache coherence protocol for chip multiprocessors.

[BibT_eX]

[DOI]

Shuchang Shan

Proceedings of the 2011 IEEE/IFIP International Conference on Dependable Systems and Networks, 2011

On diagnosis of multiple faults using compacted responses.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

Flex memory: Exploiting and managing abundant off-chip optical bandwidth.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

A cost-effective substantial-impact-filter based method to tolerate voltage emergencies.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

Cross-layer optimized placement and routing for FPGA soft error mitigation.

[BibT_eX]

[DOI]

Keheng Huang

Proceedings of the Design, Automation and Test in Europe, 2011

Eliminating data invalidation in debugging multiple-clock chips.

[BibT_eX]

[DOI]

Jianliang Gao

Proceedings of the Design, Automation and Test in Europe, 2011

Wear rate leveling: lifetime enhancement of PRAM with endurance variation.

[BibT_eX]

[DOI]

Proceedings of the 48th Design Automation Conference, 2011

Exploiting Free LUT Entries to Mitigate Soft Errors in SRAM-based FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE Asian Test Symposium, 2011

A Fault Criticality Evaluation Framework of Digital Systems for Error Tolerant Video Applications.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE Asian Test Symposium, 2011

Wrapper Chain Design for Testing TSVs Minimization in Circuit-Partitioned 3D SoC.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE Asian Test Symposium, 2011

A resilient on-chip router design through data path salvaging.

[BibT_eX]

[DOI]

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Vertical interconnects squeezing in symmetric 3D mesh Network-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010

Passive Loss Inference in Wireless Sensor Networks Using EM Algorithm.

[BibT_eX]

[DOI]

Wirel. Sens. Netw., 2010

Linear Pulse-Coupled Oscillators Model¬ - A New Approach for Time Synchronization in Wireless Sensor Networks.

[BibT_eX]

[DOI]

Wirel. Sens. Netw., 2010

X-Filling for Simultaneous Shift- and Capture-Power Reduction in At-Speed Scan-Based Testing.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2010

Performance-asymmetry-aware scheduling for Chip Multiprocessors with static core coupling.

[BibT_eX]

[DOI]

J. Syst. Archit., 2010

Extended Selective Encoding of Scan Slices for Reducing Test Data and Test Power.

[BibT_eX]

[DOI]

Jun Liu

IEICE Trans. Inf. Syst., 2010

A Novel Post-Silicon Debug Mechanism Based on Suspect Window.

[BibT_eX]

[DOI]

Jianliang Gao

IEICE Trans. Inf. Syst., 2010

Testable Critical Path Selection Considering Process Variation.

[BibT_eX]

[DOI]

Xiang Fu

IEICE Trans. Inf. Syst., 2010

Fast path selection for testing of small delay defects considering path correlations.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Improving complex distributed software system availability through information hiding.

[BibT_eX]

[DOI]

Proceedings of the 2010 ACM Symposium on Applied Computing (SAC), 2010

Address Remapping for Static NUCA in NoC-Based Degradable Chip-Multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE Pacific Rim International Symposium on Dependable Computing, 2010

nGFSIM : A GPU-based fault simulator for 1-to-n detection and its applications.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Test Conference, 2010

On generation of a universal path candidate set containing testable long paths.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Test Conference, 2010

Leveraging the core-level complementary effects of PVT variations to reduce timing emergencies in multi-core processors.

[BibT_eX]

[DOI]

Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), 2010

Performance-asymmetry-aware topology virtualization for defect-tolerant NoC-based many-core processors.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

An abstraction-guided simulation approach using Markov models for microprocessor verification.

[BibT_eX]

[DOI]

Tao Zhang

Tao Lv

Proceedings of the Design, Automation and Test in Europe, 2010

Diagnosis of multiple arbitrary faults with mask and reinforcement effect.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

An on-chip clock generation scheme for faster-than-at-speed delay testing.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

Accelerating Lightpath setup via broadcasting in binary-tree waveguide in Optical NoCs.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

Software-Based Self-Testing of Processors Using Expanded Instructions.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE Asian Test Symposium, 2010

Substantial Fault Pair At-a-Time (SFPAT): An Automatic Diagnostic Pattern Generation Method.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE Asian Test Symposium, 2010

P^(2)CLRAF: An Pre- and Post-Silicon Cooperated Circuit Lifetime Reliability Analysis Framework.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE Asian Test Symposium, 2010

An Efficient Algorithm for Finding a Universal Set of Testable Long Paths.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE Asian Test Symposium, 2010

On Selection of Testable Paths with Specified Lengths for Faster-Than-At-Speed Testing.

[BibT_eX]

[DOI]

Xiang Fu

Proceedings of the 19th IEEE Asian Test Symposium, 2010

Graph partition based path selection for testing of small delay defects.

[BibT_eX]

[DOI]

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009

On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2009

Selected Crosstalk Avoidance Code for Reliable Network-on-Chip.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2009

Preface.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2009

A sensor network performance inference algorithm based on passive measurement.

[BibT_eX]

[DOI]

Yu Yang

Yongjun Xu

Proceedings of the 2009 IEEE Wireless Communications and Networking Conference, 2009

Automatic Selection of Internal Observation Signals for Design Verification.

[BibT_eX]

[DOI]

Tao Lv

Proceedings of the 27th IEEE VLSI Test Symposium, 2009

A New Post-Silicon Debug Approach Based on Suspect Window.

[BibT_eX]

[DOI]

Jianliang Gao

Proceedings of the 27th IEEE VLSI Test Symposium, 2009

Impact of Hazards on Pattern Selection for Small Delay Defects.

[BibT_eX]

[DOI]

Proceedings of the 2009 15th IEEE Pacific Rim International Symposium on Dependable Computing, 2009

Flip-Flop Selection for Transition Test Pattern Reduction Using Partial Enhanced Scan.

[BibT_eX]

[DOI]

Proceedings of the 2009 15th IEEE Pacific Rim International Symposium on Dependable Computing, 2009

Online Computing and Predicting Architectural Vulnerability Factor of Microprocessor Structures.

[BibT_eX]

[DOI]

Songjun Pan

Proceedings of the 2009 15th IEEE Pacific Rim International Symposium on Dependable Computing, 2009

A New Multiple-Round DOR Routing for 2D Network-on-Chip Meshes.

[BibT_eX]

[DOI]

Proceedings of the 2009 15th IEEE Pacific Rim International Symposium on Dependable Computing, 2009

Variation-Aware Scheduling for Chip Multiprocessors with Thread Level Redundancy.

[BibT_eX]

[DOI]

Proceedings of the 2009 15th IEEE Pacific Rim International Symposium on Dependable Computing, 2009

MicroFix: exploiting path-grained timing adaptability for improving power-performance efficiency.

[BibT_eX]

[DOI]

Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

A unified online Fault Detection scheme via checking of Stability Violation.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

A Low Overhead On-Chip Path Delay Measurement Circuit.

[BibT_eX]

[DOI]

Proceedings of the Eighteentgh Asian Test Symposium, 2009

M-IVC: Using Multiple Input Vectors to Minimize Aging-Induced Delay.

[BibT_eX]

[DOI]

Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008

Analysis of Forwarding Mechanisms on Fine-Grain Gradient Sinking Model in WSN.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2008

Design-for-Testability Features and Test Implementation of a Giga Hertz General Purpose Microprocessor.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2008

BAT: Performance-Driven Crosstalk Mitigation Based on Bus-Grouping Asynchronous Transmission.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2008

Codeword Selection for Crosstalk Avoidance and Error Correction on Interconnects.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

Multiple Coupling Effects Oriented Path Delay Test Generation.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

Diagnosis of Mask-Effect Multiple Timing Faults in Scan Chains.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Test Conference, 2008

Deterministic Diagnostic Pattern Generation (DDPG) for Compound Defects.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Test Conference, 2008

On capture power-aware test data compression for scan-based testing.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Static Crosstalk Noise Analysis with Transition Map.

[BibT_eX]

[DOI]

Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

A Case Study on At-Speed Testing for a Gigahertz Microprocessor.

[BibT_eX]

[DOI]

Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

Adaptive Diagnostic Pattern Generation for Scan Chains.

[BibT_eX]

[DOI]

Fei Wang

Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

A Scan-Based Delay Test Method for Reduction of Overtesting.

[BibT_eX]

[DOI]

Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

Channel Width Utilization Improvement in Testing NoC-Based Systems for Test Time Reduction.

[BibT_eX]

[DOI]

Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

Defect Tolerance in Homogeneous Manycore Processors Using Core-Level Redundancy with Unified Topology.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2008

iFill: An Impact-Oriented X-Filling Method for Shift- and Capture-Power Reduction in At-Speed Scan-Based Testing.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2008

Reliable Network-on-Chip Router for Crosstalk and Soft Error Tolerance.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE Asian Test Symposium, 2008

Observation Point Oriented Deterministic Diagnosis Pattern Generation (DDPG) for Chain Diagnosis.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE Asian Test Symposium, 2008

A design- for-diagnosis technique for diagnosing both scan chain faults and combinational circuit faults.

[BibT_eX]

[DOI]

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

On reducing both shift and capture power for scan-based testing.

[BibT_eX]

[DOI]

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

Robust test generation for power supply noise induced path delay faults.

[BibT_eX]

[DOI]

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007

Embedded Test Decompressor to Reduce the Required Channels and Vector Memory of Tester for Complex Processor Circuit.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2007

Leakage Current Optimization Techniques During Test Based on Don't Care Bits Assignment.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2007

Data Mining via Minimal Spanning Tree Clustering for Prolonging Lifetime of Wireless Sensor Networks.

[BibT_eX]

[DOI]

Int. J. Inf. Technol. Decis. Mak., 2007

The design-for-testability features of a general purpose microprocessor.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE International Test Conference, 2007

Bug analysis and corresponding error models in real designs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2007

A Routing Algorithm for Random Error Tolerance in Network-on-Chip.

[BibT_eX]

[DOI]

Lei Zhang

Proceedings of the Human-Computer Interaction. HCI Applications and Services, 2007

Test Generation for Crosstalk Glitches Considering Multiple Coupling Effects.

[BibT_eX]

[DOI]

Proceedings of the 16th Asian Test Symposium, 2007

Frequency Analysis Method for Propagation of Transient Errors in Combinational Logic.

[BibT_eX]

[DOI]

Shaohua Lei

Proceedings of the 16th Asian Test Symposium, 2007

2006

Embedded test resource for SoC to reduce required tester channels based on advanced convolutional codes.

[BibT_eX]

[DOI]

IEEE Trans. Instrum. Meas., 2006

Compression/Scan Co-design for Reducing Test Data Volume, Scan-in Power Dissipation, and Test Application Time.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2006

Observability Statement Coverage Based on Dynamic Factored Use-Definition Chains for Functional Verification.

[BibT_eX]

[DOI]

J. Electron. Test., 2006

Response compaction for system-on-a-chip based on advanced convolutional codes.

[BibT_eX]

[DOI]

Sci. China Ser. F Inf. Sci., 2006

Robust Test Generation for Precise Crosstalk-induced Path Delay Faults.

[BibT_eX]

[DOI]

Pei-Fu Shen

Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

An on-chip combinational decompressor for reducing test data volume.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Clustering Versus Evenly Distributing Energy Dissipation in Wireless Sensor Routing for Prolonging Network Lifetime.

[BibT_eX]

[DOI]

Guangyan Huang

Jing He

Proceedings of the Computational Science, 2006

Fast Packet Classification using Group Bit Vector.

[BibT_eX]

[DOI]

Proceedings of the Global Telecommunications Conference, 2006. GLOBECOM '06, San Francisco, CA, USA, 27 November, 2006

An Observability Branch Coverage Metric Based on Dynamic Factored Use-Define Chains.

[BibT_eX]

[DOI]

Proceedings of the 15th Asian Test Symposium, 2006

A Scan Chain Adjustment Technology for Test Power Reduction.

[BibT_eX]

[DOI]

Jia Li

Proceedings of the 15th Asian Test Symposium, 2006

Test data compression based on clustered random access scan.

[BibT_eX]

[DOI]

Proceedings of the 15th Asian Test Symposium, 2006

A Novel Localization Scheme Based on RSS Data for Wireless Sensor Networks.

[BibT_eX]

[DOI]

Proceedings of the Advanced Web and Network Technologies, and Applications, 2006

A Lightweight Scheme for Trust Relationship Establishment in Ubiquitous Sensor Networks.

[BibT_eX]

[DOI]

Proceedings of the Sixth International Conference on Computer and Information Technology (CIT 2006), 2006

2005

An innovative free memory design for network processors in home network gateway.

[BibT_eX]

[DOI]

Shuguang Gong

IEEE Trans. Consumer Electron., 2005

An Efficient Evaluation and Vector Generation Method for Observability-Enhanced Statement Coverage.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2005

Formal Verification Techniques Based on Boolean Satisfiability Problem.

[BibT_eX]

[DOI]

Ming Shao

J. Comput. Sci. Technol., 2005

Perface.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2005

Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Tester Channels Reduction.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2005

Wrapper Scan Chains Design for Rapid and Low Power Testing of Embedded Cores.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2005

Selection of Crosstalk-Induced Faults in Enhanced Delay Test.

[BibT_eX]

[DOI]

J. Electron. Test., 2005

Compression/Scan Co-Design for Reducing Test Data Volume, Scan-in Power Dissipation and Test Application Time.

[BibT_eX]

[DOI]

Proceedings of the 11th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2005), 2005

Using MUXs Network to Hide Bunches of Scan Chains.

[BibT_eX]

[DOI]

Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Validation analysis and test flow optimization of VLSI chip.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Deterministic and low power BIST based on scan slice overlapping.

[BibT_eX]

[DOI]

Ji Li

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Non-robust Test Generation for Crosstalk-Induced Delay Faults.

[BibT_eX]

[DOI]

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

A State Machine for Detecting C/C++ Memory Faults.

[BibT_eX]

[DOI]

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

Scan Data Volume Reduction Using Periodically Alterable MUXs Decompressor.

[BibT_eX]

[DOI]

Shivakumar Swaminathan

Anshuman Chandra

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

The Automatic Generation of Basis Set of Path for Path Testing.

[BibT_eX]

[DOI]

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

Vector extraction for average total power estimation.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Theoretic analysis and enhanced X-tolerance of test response compact based on convolutional code.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Design of an efficient memory subsystem for network processor.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

Leakage Current Estimation of CMOS Circuit with Stack Effect.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2004

Conference Reports.

[BibT_eX]

IEEE Des. Test Comput., 2004

A maximum total leakage current estimation method.

[BibT_eX]

Yongjun Xu

Zuying Luo

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Response Compaction for Test Time and Test Pins Reduction Based on Advanced Convolutional Codes.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

Simultaneous Reduction of Test Data Volume and Testing Power for Scan-Based Test.

[BibT_eX]

Proceedings of the International Conference on Embedded Systems and Applications, 2004

Circuit-Width Based Heuristic for Boolean Reasoning.

[BibT_eX]

[DOI]

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

Pair Balance-Based Test Scheduling for SOCs.

[BibT_eX]

[DOI]

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

Rapid and Energy-Efficient Testing for Embedded Cores.

[BibT_eX]

[DOI]

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2003

A Novel RT-Level Behavioral Description Based ATPG Method.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2003

Average Leakage Current Macromodeling for Dual-Threshold Voltage Circuits.

[BibT_eX]

[DOI]

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

SAT-Based Algorithm of Verification for Port Order Fault.

[BibT_eX]

[DOI]

Ming Shao

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

An Efficient Observability Evaluation Algorithm Based on Factored Use-Def Chains.

[BibT_eX]

[DOI]

Tao Lv

Jianping Fan

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

Delay Test Pattern Generation Considering Crosstalk-Induced Effects.

[BibT_eX]

[DOI]

Yue Zhang

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

Design Error Diagnosis Based on Verification Techniques.

[BibT_eX]

[DOI]

Ming Shao

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Teste.

[BibT_eX]

[DOI]

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

An Expression's Single Fault Model and the Testing Methods.

[BibT_eX]

[DOI]

Yunzhan Gong

Wanli Xu

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002

The monotonic increasing relationship between average powers of CMOS VLSI circuits with and without delay and its applications.

[BibT_eX]

[DOI]

Sci. China Ser. F Inf. Sci., 2002

Test Power Optimization Techniques for CMOS Circuits.

[BibT_eX]

[DOI]

Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001

A Loop-Based Apparatus for At-Speed Self-Testing.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2001

Reducing Power Dissipation during At-Speed Test Application.

[BibT_eX]

[DOI]

Yinghua Min

Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001

An Approach to RTL Fault Extraction and Test Generation.

[BibT_eX]

[DOI]

Zhigang Yin

Yinghua Min

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

2000

Exploiting Deterministic TPG for Path Delay Testing.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2000

High Level Synthesis for Loop-Based BIST.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2000

LFSR-Based Deterministic TPG for Two-Pattern Testing.

[BibT_eX]

[DOI]

Hideo Fujiwara

J. Electron. Test., 2000

Strong self-testability for data paths high-level synthesis.

[BibT_eX]

[DOI]

Toshimitsu Masuzawa

Hideo Fujiwara

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999

An approach to behavioral synthesis for loop-based BIST.

[BibT_eX]

[DOI]

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Exploiting Test Resource Optimization in Data Path Synthesis for BIST.

[BibT_eX]

[DOI]

Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

Data Path Synthesis for BIST with Low Area Overhead.

[BibT_eX]

[DOI]

Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

1998

High-Level BIST Synthesis for Delay Testing.

[BibT_eX]

[DOI]

Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998

Exploiting BIST Approach for Two-Pattern Testing.

[BibT_eX]

[DOI]