Xiaoteng Zhao
Orcid: 0000-0002-9447-8763
According to our database1,
Xiaoteng Zhao
authored at least 17 papers
between 2019 and 2025.
Collaborative distances:
Collaborative distances:
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Bibliography
2025
A 1-V 3.9-5.2-GHz reference-sampling PLL with 168-fsrms integrated jitter and -76-dBc reference spur.
Microelectron. J., 2025
2024
A 0.08%/V 32.3-ppm/°C 36.6-kHz Unregulated Current-Reuse Ring Oscillator With VGS-Ratio-Based Compensation Using One-Type-Only Resistor.
IEEE J. Solid State Circuits, November, 2024
A 3.96-4.84-GHz Dual-Path Charge Pump PLL Achieving 89.7-fs<sub>rms</sub> Integrated Jitter and -250.8-dB FOM<sub>PLL</sub>.
IEEE Trans. Circuits Syst. II Express Briefs, April, 2024
Microelectron. J., February, 2024
A 8.1-nW, 4.22-kHz, -40-85 °C relaxation oscillator with subthreshold leakage current compensation and forward body bias buffer for low power IoT applications.
Microelectron. J., February, 2024
A low-noise, 0.05-17.8-GHz fractional-N phase-locked loop with two parallel synchronized dual-core voltage-controlled oscillators.
Microelectron. J., 2024
A 30.5-to-31 GHz Sampling PLL With Double-Edge Sampling PD and Implict Common-Mode VCO Scoring 39.69-fs RMS Jitter and -253.6-dB FoM in a 0.047mm<sup>2</sup> Area.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
2023
A 10.8-to-37.4 Gb/s Reference-Less FD-Less Single-Loop Quarter-Rate Bang-Bang Clock and Data Recovery Employing Deliberate-Current- Mismatch Wide-Frequency-Acquisition Technique.
IEEE Trans. Circuits Syst. I Regul. Pap., July, 2023
A 0.012mm<sup>2</sup> 36.41kHz Temperature-insensitive Current-Reuse Ring Oscillator Achieving 0.077%/V Line Sensitivity across a 1.3V-to-3.7V unregulated Supply.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
2022
A Sub-0.25-pJ/bit 47.6-to-58.8-Gb/s Reference-Less FD-Less Single-Loop PAM-4 Bang-Bang CDR With a Deliberate-Current-Mismatch Frequency Acquisition Technique in 28-nm CMOS.
IEEE J. Solid State Circuits, 2022
A 0.0285-mm<sup>2</sup> 0.68-pJ/bit Single-Loop Full-Rate Bang-Bang CDR Without Reference and Separate FD Pulling Off an 8.2-Gb/s/μs Acquisition Speed of the PAM-4 Input in 28-nm CMOS.
IEEE J. Solid State Circuits, 2022
A 10.8-to-37.4Gb/s Single-Loop Quarter-Rate BBCDR Without External Reference and Separate FD Featuring a Wide-Frequency-Acquisition Scheme.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022
2021
A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery (BBCDR) Circuit in 28-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
2020
A 0.0285mm<sup>2</sup> 0.68pJ/bit Single-Loop Full-Rate Bang-Bang CDR without Reference and Separate Frequency Detector Achieving an 8.2(Gb/s)/µs Acquisition Speed of PAM-4 data in 28nm CMOS.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020
2019
Analysis and Verification of Jitter in Bang-Bang Clock and Data Recovery Circuit With a Second-Order Loop Filter.
IEEE Trans. Very Large Scale Integr. Syst., 2019
A 0.0018-mm<sup>2</sup> 153% Locking-Range CML-Based Divider-by-2 With Tunable Self-Resonant Frequency Using an Auxiliary Negative-g<sub>m</sub> Cell.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery Circuit (BBCDR) in 28-nm CMOS.
Proceedings of the 2019 IEEE Asia Pacific Conference on Circuits and Systems, 2019