Xiaotao Jia
Orcid: 0000-0003-2207-6092
According to our database1,
Xiaotao Jia
authored at least 27 papers
between 2014 and 2024.
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Bibliography
2024
An Energy-Efficient Bayesian Neural Network Implementation Using Stochastic Computing Method.
IEEE Trans. Neural Networks Learn. Syst., September, 2024
DDC-PIM: Efficient Algorithm/Architecture Co-Design for Doubling Data Capacity of SRAM-Based Processing-in-Memory.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2024
CiM-BNN:Computing-in-MRAM Architecture for Stochastic Computing Based Bayesian Neural Network.
IEEE Trans. Emerg. Top. Comput., 2024
LLP-ECCA: A Low-Latency and Programmable Framework for Elliptic Curve Cryptography Accelerators.
Proceedings of the IEEE International Test Conference in Asia, 2024
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
Towards Efficient SRAM-PIM Architecture Design by Exploiting Unstructured Bit-Level Sparsity.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
2023
IMGA: Efficient In-Memory Graph Convolution Network Aggregation With Data Flow Optimizations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023
NAND-SPIN-based processing-in-MRAM architecture for convolutional neural network acceleration.
Sci. China Inf. Sci., April, 2023
"\"Peak\" Quantization: A Training Method Suitable for Terminal Equipment to Deploy Keyword Spotting Network".
Proceedings of the 4th International Conference on Artificial Intelligence and Computer Engineering, 2023
2022
Accelerating Graph-Connected Component Computation With Emerging Processing-In-Memory Architecture.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
IEEE Trans. Computers, 2022
2021
Efficient Computation Reduction in Bayesian Neural Networks Through Feature Decomposition and Memorization.
IEEE Trans. Neural Networks Learn. Syst., 2021
2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Hardware Security in Spin-based Computing-in-memory: Analysis, Exploits, and Mitigation Techniques.
ACM J. Emerg. Technol. Comput. Syst., 2020
An STT-MRAM based reconfigurable computing-in-memory architecture for general purpose computing.
CCF Trans. High Perform. Comput., 2020
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
2019
Exploiting Near-Memory Processing Architectures for Bayesian Neural Networks Acceleration.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019
2018
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
2016
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016
2015
Proceedings of the IEEE/WIC/ACM International Conference on Web Intelligence and Intelligent Agent Technology, 2015
2014
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014