Xiaoqiang Zhang
Orcid: 0000-0002-0167-6374Affiliations:
- Nanjing University, School of Electronic Science and Engineering, Nanjing, China
- Anhui Polytechnic University, College of Electrical Engineering, Wuhu, China
- Nanjing University of Aeronautics and Astronautics, College of Electrical and Information Engineering, Nanjing, China
According to our database1,
Xiaoqiang Zhang
authored at least 18 papers
between 2014 and 2022.
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Collaborative distances:
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Bibliography
2022
IEICE Electron. Express, 2022
2021
A Novel TDMA-Based Fault Tolerance Technique for the TSVs in 3D-ICs Using Honeycomb Topology.
IEEE Trans. Emerg. Top. Comput., 2021
2020
A low critical path delay structure for composite field AES S-box based on constant matrices multiplication merging.
IEICE Electron. Express, 2020
A full matrix joint optimization method for hardware implementation of AES MixColumns/InvMixColumns.
IEICE Electron. Express, 2020
2019
IEICE Electron. Express, 2019
Poet: A Power Efficient Hybrid Optical NoC Topology for Heterogeneous CPU-GPU Systems.
Proceedings of the IECON 2019, 2019
2018
An Optimized Design for Compact Masked AES S-Box Based on Composite Field and Common Subexpression Elimination Algorithm.
J. Circuits Syst. Comput., 2018
J. Circuits Syst. Comput., 2018
High performance AES-GCM implementation based on efficient AES and FR-KOA multiplier.
IEICE Electron. Express, 2018
Research on physical unclonable functions circuit based on three dimensional integrated circuit.
IEICE Electron. Express, 2018
2017
IEICE Electron. Express, 2017
2016
Optimization of Area and Delay for Implementation of the Composite Field Advanced Encryption Standard S-Box.
J. Circuits Syst. Comput., 2016
IEICE Electron. Express, 2016
IEICE Electron. Express, 2016
2015
High-performance adaptive hybrid wireless NoC architecture based on improved congestion measurement.
IEICE Electron. Express, 2015
An evolutionary algorithm based on novel hybrid repair strategy for combinational logic circuits.
IEICE Electron. Express, 2015
2014
An optimized delay-aware common subexpression elimination algorithm for hardware implementation of binary-field linear transform.
IEICE Electron. Express, 2014