Xiaonan Tian

According to our database1, Xiaonan Tian authored at least 13 papers between 2012 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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On csauthors.net:

Bibliography

2024
Predictive value of dynamic diffusion tensor imaging for surgical outcomes in patients with cervical spondylotic myelopathy.
BMC Medical Imaging, December, 2024

2018
The OpenACC data model: Preliminary study on its major challenges and implementations.
Parallel Comput., 2018

2017
Assessing One-to-One Parallelism Levels Mapping for OpenMP Offloading to GPUs.
Proceedings of the 8th International Workshop on Programming Models and Applications for Multicores and Manycores, 2017

Implementing the OpenACC Data Model.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017

2016
Compiler transformation of nested loops for general purpose GPUs.
Concurr. Comput. Pract. Exp., 2016

An Analytical Model-Based Auto-tuning Framework for Locality-Aware Loop Scheduling.
Proceedings of the High Performance Computing - 31st International Conference, 2016

Optimizing GPU Register Usage: Extensions to OpenACC and Compiler Optimizations.
Proceedings of the 45th International Conference on Parallel Processing, 2016

2015
Multi-GPU Support on Single Node Using Directive-Based Programming Model.
Sci. Program., 2015

2014
Reduction Operations in Parallel Loops for GPGPUs.
Proceedings of the 2014 PPOPP International Workshop on Programming Models and Applications for Multicores and Manycores, 2014

NAS Parallel Benchmarks for GPGPUs Using a Directive-Based Programming Model.
Proceedings of the Languages and Compilers for Parallel Computing, 2014

2013
Compiling a High-Level Directive-Based Programming Model for GPGPUs.
Proceedings of the Languages and Compilers for Parallel Computing, 2013

2012
Performance and Power Characteristics of Matrix Multiplication Algorithms on Multicore and Shared Memory Machines.
Proceedings of the 2012 SC Companion: High Performance Computing, 2012

Acceleration of bulk memory operations in a heterogeneous multicore architecture.
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012


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