Xiaolin Xu
Orcid: 0000-0001-8393-2783Affiliations:
- Northeastern University, Boston, MA, USA
- University of Illinois Chicago, IL, USA (2018 - 2020)
- University of Florida Gainesville, FL, USA (2016 - 2018)
- University of Massachusetts Amherst, MA, USA (PhD 2016)
According to our database1,
Xiaolin Xu
authored at least 80 papers
between 2013 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
AdaPI: Facilitating DNN Model Adaptivity for Efficient Private Inference in Edge Computing.
CoRR, 2024
SSNet: A Lightweight Multi-Party Computation Scheme for Practical Privacy-Preserving Machine Learning Service in the Cloud.
CoRR, 2024
Bileve: Securing Text Provenance in Large Language Models Against Spoofing with Bi-level Signature.
CoRR, 2024
Scheduled Knowledge Acquisition on Lightweight Vector Symbolic Architectures for Brain-Computer Interfaces.
CoRR, 2024
Proceedings of the 2024 IEEE Symposium on Visual Languages and Human-Centric Computing (VL/HCC), 2024
DeepShuffle: A Lightweight Defense Framework against Adversarial Fault Injection Attacks on Deep Neural Networks in Multi-Tenant Cloud-FPGA.
Proceedings of the IEEE Symposium on Security and Privacy, 2024
Side-Channel-Assisted Reverse-Engineering of Encrypted DNN Hardware Accelerator IP and Attack Surface Exploration.
Proceedings of the IEEE Symposium on Security and Privacy, 2024
ArchLock: Locking DNN Transferability at the Architecture Level with a Zero-Cost Binary Predictor.
Proceedings of the Twelfth International Conference on Learning Representations, 2024
TBNet: A Neural Architectural Defense Framework Facilitating DNN Model Protection in Trusted Execution Environments.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
MicroVSA: An Ultra-Lightweight Vector Symbolic Architecture-based Classifier Library for Always-On Inference on Tiny Microcontrollers.
Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2024
2023
NNSplitter: An Active Defense Solution to DNN Model via Automated Weight Obfuscation.
CoRR, 2023
MetaLDC: Meta Learning of Low-Dimensional Computing Classifiers for Fast On-Device Adaption.
CoRR, 2023
RRNet: Towards ReLU-Reduced Neural Network for Two-party Computation Based Private Inference.
CoRR, 2023
LinGCN: Structural Linearized Graph Convolutional Network for Homomorphically Encrypted Inference.
Proceedings of the Advances in Neural Information Processing Systems 36: Annual Conference on Neural Information Processing Systems 2023, 2023
AQ2PNN: Enabling Two-party Privacy-Preserving Deep Neural Network Inference with Adaptive Quantization.
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023
Achieving Certified Robustness for Brain-Inspired Low-Dimensional Computing Classifiers.
Proceedings of the IEEE INFOCOM 2023, 2023
NNSplitter: An Active Defense Solution for DNN Model via Automated Weight Obfuscation.
Proceedings of the International Conference on Machine Learning, 2023
SpENCNN: Orchestrating Encoding and Sparsity for Fast Homomorphically Encrypted Neural Network Inference.
Proceedings of the International Conference on Machine Learning, 2023
Proceedings of the IEEE/CVF International Conference on Computer Vision, 2023
Proceedings of the IEEE/CVF International Conference on Computer Vision, 2023
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023
PASNet: Polynomial Architecture Search Framework for Two-party Computation-based Secure Neural Network Deployment.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
2022
ACM Trans. Design Autom. Electr. Syst., 2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
CoRR, 2022
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022
Proceedings of the International Conference on Field-Programmable Technology, 2022
Proceedings of the FPGA '22: The 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Virtual Event, USA, 27 February 2022, 2022
NNReArch: A Tensor Program Scheduling Framework Against Neural Network Architecture Reverse Engineering.
Proceedings of the 30th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2022
HDLock: exploiting privileged encoding to protect hyperdimensional computing models against IP stealing.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
2021
Deep-Dup: An Adversarial Weight Duplication Attack Framework to Crush Deep Neural Network in Multi-Tenant FPGA.
Proceedings of the 30th USENIX Security Symposium, 2021
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2021
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2021
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021
Constructive Use of Process Variations: Reconfigurable and High-Resolution Delay-Line.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
DeepStrike: Remotely-Guided Fault Injection Attacks on DNN Accelerator in Cloud-FPGA.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
2020
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2020
IEEE Trans. Circuits Syst., 2020
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020
Proceedings of the 38th IEEE International Conference on Computer Design, 2020
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020
A Dynamic Frequency Scaling Framework Against Reliability and Security Issues in Multi-tenant FPGA.
Proceedings of the 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2020
2019
ACM Trans. Design Autom. Electr. Syst., 2019
EOP: An Encryption-Obfuscation Solution for Protecting PCBs Against Tampering and Reverse Engineering.
CoRR, 2019
PVTMC: An All-Digital Sub-Picosecond Timing Measurement Circuit Based on Process Variations.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019
HILL: A Hardware Isolation Framework Against Information Leakage on Multi-Tenant FPGA Long-Wires.
Proceedings of the International Conference on Field-Programmable Technology, 2019
An All-Digital True Random Number Generator Based on Chaotic Cellular Automata Topology.
Proceedings of the International Conference on Computer-Aided Design, 2019
2018
IEEE Trans. Very Large Scale Integr. Syst., 2018
IEEE Trans. Very Large Scale Integr. Syst., 2018
Survey on Applications of Formal Methods in Reverse Engineering and Intellectual Property Protection.
J. Hardw. Syst. Secur., 2018
J. Hardw. Syst. Secur., 2018
IACR Cryptol. ePrint Arch., 2018
Proceedings of the 55th Annual Design Automation Conference, 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
Novel Bypass Attack and BDD-based Tradeoff Analysis Against all Known Logic Locking Attacks.
IACR Cryptol. ePrint Arch., 2017
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017
Proceedings of the 54th Annual Design Automation Conference, 2017
Proceedings of the 2017 Asian Hardware Oriented Security and Trust Symposium, 2017
2016
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016
Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016
2015
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
IACR Cryptol. ePrint Arch., 2015
PLayPUF: Programmable Logically Erasable PUFs for Forward and Backward Secure Key Management.
IACR Cryptol. ePrint Arch., 2015
Proceedings of the 2015 IEEE Symposium on Security and Privacy, 2015
2014
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2014, 2014
2013
IEEE Trans. Inf. Forensics Secur., 2013
IACR Cryptol. ePrint Arch., 2013