Xiaolin Xu

Orcid: 0000-0001-8393-2783

Affiliations:
  • Northeastern University, Boston, MA, USA
  • University of Illinois Chicago, IL, USA (2018 - 2020)
  • University of Florida Gainesville, FL, USA (2016 - 2018)
  • University of Massachusetts Amherst, MA, USA (PhD 2016)


According to our database1, Xiaolin Xu authored at least 80 papers between 2013 and 2024.

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Timeline

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Bibliography

2024
AdaPI: Facilitating DNN Model Adaptivity for Efficient Private Inference in Edge Computing.
CoRR, 2024

SSNet: A Lightweight Multi-Party Computation Scheme for Practical Privacy-Preserving Machine Learning Service in the Cloud.
CoRR, 2024

Bileve: Securing Text Provenance in Large Language Models Against Spoofing with Bi-level Signature.
CoRR, 2024

Scheduled Knowledge Acquisition on Lightweight Vector Symbolic Architectures for Brain-Computer Interfaces.
CoRR, 2024

ALLI/O Diagram: An Action-based Visual Programming Language for Embedded System.
Proceedings of the 2024 IEEE Symposium on Visual Languages and Human-Centric Computing (VL/HCC), 2024

DeepShuffle: A Lightweight Defense Framework against Adversarial Fault Injection Attacks on Deep Neural Networks in Multi-Tenant Cloud-FPGA.
Proceedings of the IEEE Symposium on Security and Privacy, 2024

Side-Channel-Assisted Reverse-Engineering of Encrypted DNN Hardware Accelerator IP and Attack Surface Exploration.
Proceedings of the IEEE Symposium on Security and Privacy, 2024

ArchLock: Locking DNN Transferability at the Architecture Level with a Zero-Cost Binary Predictor.
Proceedings of the Twelfth International Conference on Learning Representations, 2024

TBNet: A Neural Architectural Defense Framework Facilitating DNN Model Protection in Trusted Execution Environments.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

MicroVSA: An Ultra-Lightweight Vector Symbolic Architecture-based Classifier Library for Always-On Inference on Tiny Microcontrollers.
Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2024

2023
NNSplitter: An Active Defense Solution to DNN Model via Automated Weight Obfuscation.
CoRR, 2023

MetaLDC: Meta Learning of Low-Dimensional Computing Classifiers for Fast On-Device Adaption.
CoRR, 2023

RRNet: Towards ReLU-Reduced Neural Network for Two-party Computation Based Private Inference.
CoRR, 2023

LinGCN: Structural Linearized Graph Convolutional Network for Homomorphically Encrypted Inference.
Proceedings of the Advances in Neural Information Processing Systems 36: Annual Conference on Neural Information Processing Systems 2023, 2023

AQ2PNN: Enabling Two-party Privacy-Preserving Deep Neural Network Inference with Adaptive Quantization.
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

Achieving Certified Robustness for Brain-Inspired Low-Dimensional Computing Classifiers.
Proceedings of the IEEE INFOCOM 2023, 2023

NNSplitter: An Active Defense Solution for DNN Model via Automated Weight Obfuscation.
Proceedings of the International Conference on Machine Learning, 2023

SpENCNN: Orchestrating Encoding and Sparsity for Fast Homomorphically Encrypted Neural Network Inference.
Proceedings of the International Conference on Machine Learning, 2023

AutoReP: Automatic ReLU Replacement for Fast Private Network Inference.
Proceedings of the IEEE/CVF International Conference on Computer Vision, 2023

VertexSerum: Poisoning Graph Neural Networks for Link Inference.
Proceedings of the IEEE/CVF International Conference on Computer Vision, 2023

MirrorNet: A TEE-Friendly Framework for Secure On-Device DNN Inference.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

PASNet: Polynomial Architecture Search Framework for Two-party Computation-based Secure Neural Network Deployment.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

HammerDodger: A Lightweight Defense Framework against RowHammer Attack on DNNs.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022
FPGAPRO: A Defense Framework Against Crosstalk-Induced Secret Leakage in FPGA.
ACM Trans. Design Autom. Electr. Syst., 2022

CRAlert: Hardware-Assisted Code Reuse Attack Detection.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

FLAM-PUF: A Response-Feedback-Based Lightweight Anti-Machine-Learning-Attack PUF.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

STT-MRAM-Based Reliable Weak PUF.
IEEE Trans. Computers, 2022

A Brain-Inspired Low-Dimensional Computing Classifier for Inference on Tiny Devices.
CoRR, 2022

ObfuNAS: A Neural Architecture Search-Based DNN Obfuscation Approach.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

A Cautionary Note on Building Multi-tenant Cloud-FPGA as a Secure Infrastructure.
Proceedings of the International Conference on Field-Programmable Technology, 2022

An Integrity Checking Framework for AXI Protocol in Multi-tenant FPGA.
Proceedings of the FPGA '22: The 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Virtual Event, USA, 27 February 2022, 2022

NNReArch: A Tensor Program Scheduling Framework Against Neural Network Architecture Reverse Engineering.
Proceedings of the 30th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2022

HDLock: exploiting privileged encoding to protect hyperdimensional computing models against IP stealing.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

LeHDC: learning-based hyperdimensional computing classifier.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021
Deep-Dup: An Adversarial Weight Duplication Attack Framework to Crush Deep Neural Network in Multi-Tenant FPGA.
Proceedings of the 30th USENIX Security Symposium, 2021

Deep Neural Network Security From a Hardware Perspective.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2021

HDCOG: A Lightweight Hyperdimensional Computing Framework with Feature Extraction.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2021

A Survey of Recent Attacks and Mitigation on FPGA Systems.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

Constructive Use of Process Variations: Reconfigurable and High-Resolution Delay-Line.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

SGX-FPGA: Trusted Execution Environment for CPU-FPGA Heterogeneous Architecture.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

DeepStrike: Remotely-Guided Fault Injection Attacks on DNN Accelerator in Cloud-FPGA.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020
CAS-Lock: A Security-Corruptibility Trade-off Resilient Logic Locking Scheme.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2020

A High-Performance and Secure TRNG Based on Chaotic Cellular Automata Topology.
IEEE Trans. Circuits Syst., 2020

Defeating CAS-Unlock.
IACR Cryptol. ePrint Arch., 2020

A Privacy-Preserving DNN Pruning and Mobile Acceleration Framework.
CoRR, 2020

Rethinking FPGA Security in the New Era of Artificial Intelligence.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

Stealthy-Shutdown: Practical Remote Power Attacks in Multi - Tenant FPGAs.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020

A Quantitative Defense Framework against Power Attacks on Multi-tenant FPGA.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

A Privacy-Preserving-Oriented DNN Pruning and Mobile Acceleration Framework.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

A Dynamic Frequency Scaling Framework Against Reliability and Security Issues in Multi-tenant FPGA.
Proceedings of the 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2020

2019
Electronics Supply Chain Integrity Enabled by Blockchain.
ACM Trans. Design Autom. Electr. Syst., 2019

EOP: An Encryption-Obfuscation Solution for Protecting PCBs Against Tampering and Reverse Engineering.
CoRR, 2019

PVTMC: An All-Digital Sub-Picosecond Timing Measurement Circuit Based on Process Variations.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

HILL: A Hardware Isolation Framework Against Information Leakage on Multi-Tenant FPGA Long-Wires.
Proceedings of the International Conference on Field-Programmable Technology, 2019

An All-Digital True Random Number Generator Based on Chaotic Cellular Automata Topology.
Proceedings of the International Conference on Computer-Aided Design, 2019

2018
Bimodal Oscillation as a Mechanism for Autonomous Majority Voting in PUFs.
IEEE Trans. Very Large Scale Integr. Syst., 2018

SCARe: An SRAM-Based Countermeasure Against IC Recycling.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Survey on Applications of Formal Methods in Reverse Engineering and Intellectual Property Protection.
J. Hardw. Syst. Secur., 2018

Development and Evaluation of Hardware Obfuscation Benchmarks.
J. Hardw. Syst. Secur., 2018

Efficient Erasable PUFs from Programmable Logic and Memristors.
IACR Cryptol. ePrint Arch., 2018

Power-based side-channel instruction-level disassembler.
Proceedings of the 55th Annual Design Automation Conference, 2018

2017
Poly-Si-Based Physical Unclonable Functions.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Security Beyond CMOS: Fundamentals, Applications, and Roadmap.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Novel Bypass Attack and BDD-based Tradeoff Analysis Against all Known Logic Locking Attacks.
IACR Cryptol. ePrint Arch., 2017

Aging resilient RO PUF with increased reliability in FPGA.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017

CCATDC: A Configurable Compact Algorithmic Time-to-Digital Converter.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

FFD: A Framework for Fake Flash Detection.
Proceedings of the 54th Annual Design Automation Conference, 2017

MPA: Model-assisted PCB attestation via board-level RO and temperature compensation.
Proceedings of the 2017 Asian Hardware Oriented Security and Trust Symposium, 2017

2016
Using Statistical Models to Improve the Reliability of Delay-Based PUFs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

A Clockless Sequential PUF with Autonomous Majority Voting.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Reliable PUF design using failure patterns from time-controlled power gating.
Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016

2015
Reliable Physical Unclonable Functions Using Data Retention Voltage of SRAM Cells.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Security Evaluation and Enhancement of Bistable Ring PUFs.
IACR Cryptol. ePrint Arch., 2015

PLayPUF: Programmable Logically Erasable PUFs for Forward and Backward Secure Key Management.
IACR Cryptol. ePrint Arch., 2015

Virtual Proofs of Reality and their Physical Implementation.
Proceedings of the 2015 IEEE Symposium on Security and Privacy, 2015

2014
Post-Silicon Validation and Calibration of Hardware Security Primitives.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Hybrid side-channel/machine-learning attacks on PUFs: A new threat?
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Efficient Power and Timing Side Channels for Physical Unclonable Functions.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2014, 2014

2013
PUF Modeling Attacks on Simulated and Silicon Data.
IEEE Trans. Inf. Forensics Secur., 2013

Power and Timing Side Channels for PUFs and their Efficient Exploitation.
IACR Cryptol. ePrint Arch., 2013


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