Xiaole Cui

According to our database, Xiaole Cui authored at least 71 papers between 2006 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

An in-Array Build-In Self-Test Scheme for Embedded SRAM Array.

Feng Wei, Xiaole Cui, Sunrui Zhang

IEEE Trans. Circuits Syst. II Express Briefs, August, 2024

An 11T SRAM Cell for the Dual-Direction In-Array Logic/CAM Operations.

Feng Wei, Xiaole Cui, Sunrui Zhang, Xing Zhang

IEEE Trans. Circuits Syst. II Express Briefs, April, 2024

Dy-MFNS-CAC: An Encoding Mechanism to Suppress the Crosstalk and Repair the Hard Faults in Rectangular TSV Arrays.

Chen Wei, Xiaole Cui, Xiaoxin Cui

IEEE Trans. Reliab., March, 2024

The area-efficient gate level information flow tracking schemes of digital circuit with multi-level security lattice.

Yongliang Chen, Xiaole Cui, Xiaoxin Cui, Xing Zhang

Microelectron. J., February, 2024

The Resistance Analysis Attack and Security Enhancement of the IMC LUT Based on the Complementary Resistive Switch Cells.

Xiaole Cui, Mingqi Yin, Hanqing Liu, Xiaoxin Cui

ACM Trans. Design Autom. Electr. Syst., January, 2024

A reconfigurable FPGA-based spiking neural network accelerator.

Mingqi Yin, Xiaole Cui, Feng Wei, Hanqing Liu, Yuanyuan Jiang, Xiaoxin Cui

Microelectron. J., 2024

A High Performance PODEM Algorithm with the Improved Backtrace Process.

Yang Zeng, Xiaole Cui

Proceedings of the IEEE International Test Conference in Asia, 2024

SPAT: FPGA-based Sparsity-Optimized Spiking Neural Network Training Accelerator with Temporal Parallel Dataflow.

Yuanyuan Jiang, Li Lun, Jiawei Wang, Mingqi Yin, Hanqing Liu, Zhenhui Dai, Xiaole Cui, Xiaoxin Cui

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

Modeling Attack Tests and Security Enhancement of the Sub-Threshold Voltage Divider Array PUF.

Shengjie Zhou, Yongliang Chen, Xiaole Cui, Yun Liu

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

A Convolutional Spiking Neural Network Accelerator with the Sparsity-Aware Memory and Compressed Weights.

Hanqing Liu, Xiaole Cui, Sunrui Zhang, Mingqi Yin, Yuanyuan Jiang, Xiaoxin Cui

Proceedings of the 35th IEEE International Conference on Application-specific Systems, 2024

2023

An Area-Efficient In-Memory Implementation Method of Arbitrary Boolean Function Based on SRAM Array.

Sunrui Zhang, Xiaole Cui, Feng Wei, Xiaoxin Cui

IEEE Trans. Computers, December, 2023

Mosaic-3C1S: A Low Overhead Crosstalk Suppression Scheme for Rectangular TSV Array.

Xiaole Cui, Chen Wei, Xu Feng, Xiaoxin Cui

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., May, 2023

An Evaluation Method of the Anti-Modeling-Attack Capability of PUFs.

Yongliang Chen, Xiaole Cui, Yun Liu, Xiaoxin Cui

IEEE Trans. Inf. Forensics Secur., 2023

An Anti-Removal-Attack Hardware Watermarking Method Based on Polymorphic Gates.

Yongliang Chen, Xiaole Cui, Pengyuan Yang, Gang Qu

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

2022

A Global Self-Repair Method for TSV Arrays With Adaptive FNS-CAC Codec.

Chen Wei, Xiaole Cui, Xiaoxin Cui

IEEE Des. Test, 2022

An Area-Efficient and Robust Memristive LUT Based on the Enhanced Scouting Logic Cells.

Xiaole Cui, Fan Liu, Sunrui Zhang, Xiaoxin Cui

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A Modeling Attack on the Sub-threshold Current Array PUF.

Yun Liu, Yongliang Chen, Xiaole Cui

Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2022

The Design Method of Logic Circuits based on the Voltage-Input Enhanced Scouting Logic Gates.

Fan Liu, Sunrui Zhang, Xiaole Cui

Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022

An obfuscation scheme of scan chain to protect the cryptographic chips.

Huixian Huang, Xiaole Cui, Shuming Zhang, Ge Li, Xiaoxin Cui

Proceedings of the IEEE 31st Asian Test Symposium, 2022

2021

Machine Learning Aided Key-Guessing Attack Paradigm Against Logic Block Encryption.

Yi Zhong, Jianhua Feng, Xiaoxin Cui, Xiaole Cui

J. Comput. Sci. Technol., 2021

28nm asynchronous area-saving AES processor with high Common and Machine learning side-channel attack resistance.

Qingyun Zou, Xiaoxin Cui, Zhenhui Dai, Yisong Kuang, Yi Zhong, Chenglong Zou, Xiaole Cui

IEICE Electron. Express, 2021

The Synthesis Method of Logic Circuits Based on the NMOS-Like RRAM Gates.

Xiaole Cui, Ye Ma, Feng Wei, Xiaoxin Cui

IEEE Access, 2021

The Security Enhancement Techniques of the Double-layer PUF Against the ANN-based Modeling Attack.

Yongliang Chen, Xiaole Cui, Wenqiang Ye, Xiaoxin Cui

Proceedings of the IEEE International Test Conference, 2021

The ANN Based Modeling Attack and Security Enhancement of the Double-layer PUF.

Xiaole Cui, Yongliang Chen, Wenqiang Ye, Xiaoxin Cui

Proceedings of the IEEE International Test Conference in Asia, 2021

An SNN-Based and Neuromorphic-Hardware-Implementable Noise Filter with Self-adaptive Time Window for Event-Based Vision Sensor.

Kanglin Xiao, Xiaoxin Cui, Kefei Liu, Xiaole Cui, Xin'an Wang

Proceedings of the International Joint Conference on Neural Networks, 2021

The Modeling Attack and Security Enhancement of the XbarPUF with Both Column Swapping and XORing.

Yongliang Chen, Xiaole Cui, Wenqiang Ye, Xiaoxin Cui

Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

Design and Implementation of Full Adder in One-Transistor-One-Resistor RRAM Array.

Xiangyu Zhang, Feng Wei, Xiaoyan Liu, Xiaole Cui

Proceedings of the 14th IEEE International Conference on ASIC, 2021

The logic obfuscation of LFSR with the crosstalk based polymorphic gate.

Yuqian Sun, Xiaole Cui, Yongliang Chen, Xiaoxin Cui

Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2021

2020

The synthesis method of logic circuits based on the iMemComp gates.

Xiaole Cui, Qiujun Lin, Xiaoxin Cui, Feng Wei, Xiaoyan Liu, Jinfeng Kang

Integr., 2020

Design of High-Speed Logic Circuits with Four-Step RRAM-Based Logic Gates.

Xiaole Cui, Xiao Ma, Qiujun Lin, Xiang Li, Hang Zhou, Xiaoxin Cui

Circuits Syst. Signal Process., 2020

A synthesis method for logic circuits in RRAM arrays.

Xiaole Cui, Xiao Ma, Feng Wei, Xiaoxin Cui

Sci. China Inf. Sci., 2020

ReTriple: Reduction of Redundant Rendering on Android Devices for Performance and Energy Optimizations.

Xianfeng Li, Gengchao Li, Xiaole Cui

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

A Testability Enhancement Method for the Memristor Ratioed Logic Circuits.

Li Qu, Xiaole Cui, Xiaoxin Cui

Proceedings of the 29th IEEE Asian Test Symposium, 2020

2019

Efficient evaluation model including interconnect resistance effect for large scale RRAM crossbar array matrix computing.

Runze Han, Peng Huang, Yudi Zhao, Xiaole Cui, Xiaoyan Liu, Jinfeng Kang

Sci. China Inf. Sci., 2019

Flash-based Computing in-Memory Scheme for IOT.

Jinfeng Kang, Peng Huang, Runze Han, Yachen Xiang, Xiaole Cui, Xiaoyan Liu

Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018

Evaluation of Dynamic-Adjusting Threshold-Voltage Scheme for Low-Power FinFET Circuits.

Tian Wang, Xiaoxin Cui, Yewen Ni, Dunshan Yu, Xiaole Cui

IEEE Trans. Very Large Scale Integr. Syst., 2018

Design of Low-Power High-Performance FinFET Standard Cells.

Tian Wang, Xiaoxin Cui, Kai Liao, Nan Liao, Dunshan Yu, Xiaole Cui

Circuits Syst. Signal Process., 2018

A Novel Polymorphic Gate Based Circuit Fingerprinting Technique.

Tian Wang, Xiaoxin Cui, Dunshan Yu, Omid Aramoon, Timothy Dunlap, Gang Qu, Xiaole Cui

Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

Polymorphic gate based IC watermarking techniques.

Tian Wang, Xiaoxin Cui, Dunshan Yu, Omid Aramoon, Timothy Dunlap, Gang Qu, Xiaole Cui

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017

An Enhancement of Crosstalk Avoidance Code Based on Fibonacci Numeral System for Through Silicon Vias.

Xiaole Cui, Xiaoxin Cui, Yewen Ni, Min Miao, Yufeng Jin

IEEE Trans. Very Large Scale Integr. Syst., 2017

High-Performance Noninvasive Side-Channel Attack Resistant ECC Coprocessor for GF(2m ).

Kai Liao, Xiaoxin Cui, Nan Liao, Tian Wang, Dunshan Yu, Xiaole Cui

IEEE Trans. Ind. Electron., 2017

Improving DFA attacks on AES with unknown and random faults.

Nan Liao, Xiaoxin Cui, Kai Liao, Tian Wang, Dunshan Yu, Xiaole Cui

Sci. China Inf. Sci., 2017

Testing of 1T<i>n</i>R RRAM array with sneak path technique.

Xiaole Cui, Qiang Zhang, Xiaoxin Cui, Xin'an Wang, Jinfeng Kang, Xiaoyan Liu

Sci. China Inf. Sci., 2017

A new calibration method for MEMS accelerometers with genetic algorithm.

Xiaole Cui, Chunliang Liu, Guangyi Shi, Yufeng Jin

Proceedings of the 2017 IEEE International Conference on Real-time Computing and Robotics, 2017

A Heuristic Algorithm for Automatic Generation of March Tests.

Xiaole Cui, Yichi Luo, Qiujun Lin, Xiaoxin Cui

Proceedings of the 26th IEEE Asian Test Symposium, 2017

A signal noise separation method for the instant mixing linear and nonlinear circuits with MISEP algorithm.

Liwen Zhu, Xiaole Cui, Xiang Li, Xiaoxin Cui

Proceedings of the 12th IEEE International Conference on ASIC, 2017

A design of high performance full adder with memristors.

Kuimin Zhang, Xiaole Cui, Xiaoxin Cui

Proceedings of the 12th IEEE International Conference on ASIC, 2017

Improving DFA on AES using all-fault ciphertexts.

Yewen Ni, Xiaoxin Cui, Tian Wang, Yuanning Fan, Qiankun Han, Kefei Liu, Xiaole Cui

Proceedings of the 12th IEEE International Conference on ASIC, 2017

Design of router for spiking neural networks.

Yewen Ni, Xiaoxin Cui, Yuanning Fan, Qiankun Han, Kefei Liu, Xiaole Cui

Proceedings of the 12th IEEE International Conference on ASIC, 2017

A practical cold boot attack on RSA private keys.

Tian Wang, Xiaoxin Cui, Yewen Ni, Dunshan Yu, Xiaole Cui, Gang Qu

Proceedings of the 2017 Asian Hardware Oriented Security and Trust Symposium, 2017

2016

Low Power High Performance FinFET Standard Cells Based on Mixed Back Biasing Technology.

Tian Wang, Xiaoxin Cui, Kai Liao, Nan Liao, Xiaole Cui, Dunshan Yu

IEICE Trans. Electron., 2016

Ultralow-power high-speed flip-flop based on multimode FinFETs.

Kai Liao, Xiaoxin Cui, Nan Liao, Tian Wang, Dunshan Yu, Xiaole Cui

Sci. China Inf. Sci., 2016

A snake addressing scheme for phase change memory testing.

Xiaole Cui, Zuolin Cheng, Chung-Len Lee, Xinnan Lin, Yiqun Wei, Xiaogang Chen, Zhitang Song

Sci. China Inf. Sci., 2016

2015

Self-heating burn-in pattern generation based on the genetic algorithm incorporated with a BACK-like procedure.

Zuolin Cheng, Xiaole Cui, Xiaoxin Cui, Chung Len Lee

IET Comput. Digit. Tech., 2015

Context-adaptive fast motion estimation of HEVC.

Xufeng Li, Ronggang Wang, Xiaole Cui, Wenmin Wang

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A TSV repair method for clustered faults.

Shijie Zhang, Xiaole Cui, Qiang Zhang, Yufeng Jin

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

An enhanced decoder for multiple-bit error correcting BCH codes.

Hupo Wei, Xiaole Cui, Qiang Zhang, Yufeng Jin

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

Employing the mixed FBB/RBB in the design of FinFET logic gates.

Tian Wang, Xiaoxin Cui, Kai Liao, Nan Liao, Yewen Ni, Dunshan Yu, Xiaole Cui

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

A countermeasure for power analysis to scalar multiplication of ECC hardware.

Lifei Liu, Xiaole Cui, Yalin Ran, Xiaoxin Cui

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

A high-efficient and accurate fault model aiming at FPGA-based AES cryptographic applications.

Nan Liao, Xiaoxin Cui, Tian Wang, Kai Liao, Yewen Ni, Dunshan Yu, Xiaole Cui

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

Post-bond test for TSVs using voltage division.

Bingqiang Jing, Xiaole Cui, Yalin Ran, Yufeng Jin

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2013

A UWB mixer with a balanced wide band active balun using crossing centertaped inductor.

Xiangrong Zhang, Xiaole Cui, Bo Wang, Chung Len Lee

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A test pattern selection method for dynamic burn-in of logic circuits based on ATPG technique.

Xuan Yang, Xiaole Cui, Chao Wang, Chung Len Lee

Proceedings of the IEEE 10th International Conference on ASIC, 2013

A folded current-reused CMOS power amplifier for low-voltage 3.0-5.0 GHz UWB applications.

Zhengyu Qian, Xiaole Cui, Bo Wang, Xiangrong Zhang, Chung Len Lee

Proceedings of the IEEE 10th International Conference on ASIC, 2013

Enhanced error correction against multiple-bit-upset based on BCH code for SRAM.

Weijia Ma, Xiaole Cui, Chung Len Lee

Proceedings of the IEEE 10th International Conference on ASIC, 2013

New DfT architectures for 3D-SICs with a wireless test port.

Yibo He, Xiaole Cui, Chung Len Lee, Xiaoxin Cui, Yufeng Jin

Proceedings of the IEEE 10th International Conference on ASIC, 2013

AHardware implementation of DES with combined countermeasure against DPA.

Xiaoxin Cui, Rui Li, Wei Wei, Juan Gu, Xiaole Cui

Proceedings of the IEEE 10th International Conference on ASIC, 2013

A novel test scheme for NAND flash memory based on built-in oscillator ring.

Si Chen, Xiaole Cui, Chung Len Lee

Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012

Modeling and testing of interference faults in the nano NAND Flash memory.

Jin Zha, Xiaole Cui, Chung Len Lee

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2008

Towards HMM based human motion recognition using MEMS inertial sensors.

Guangyi Shi, Yuexian Zou, Yufeng Jin, Xiaole Cui, Wen Jung Li

Proceedings of the IEEE International Conference on Robotics and Biomimetics, 2008

2006

Design and Implementation of a 2-level FSK Digital Modems Using CORDIC Algorithm.

Xiaoxin Cui, Dunshan Yu, Shimin Sheng, Xiaole Cui

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006