Xiaojun Wang

Orcid: 0000-0002-1665-4629

Affiliations:
  • Beijing Institute of Technology, School of Computer Science and Technology, China


According to our database1, Xiaojun Wang authored at least 9 papers between 2014 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2021
KGT: An Application Mapping Algorithm Based on Kernighan-Lin Partition and Genetic Algorithm for WK-Recursive NoC Architecture.
Proceedings of the Intelligent Computing Theories and Application, 2021

2019
A Novel Speedup Evaluation for Multicore Architecture Based Topology of On-Chip Memory.
Proceedings of the Parallel Architectures, Algorithms and Programming, 2019

KLSAT: An Application Mapping Algorithm Based on Kernighan-Lin Partition and Simulated Annealing for a Specific WK-Recursive NoC Architecture.
Proceedings of the Network and Parallel Computing, 2019

2018
Power-aware high level evaluation model of interconnect length of on-chip memory network topology.
Int. J. Comput. Sci. Eng., 2018

A novel look-ahead routing algorithm based on graph theory for triplet-based network-on-chip router.
IEICE Electron. Express, 2018

An Efficient Distributed Minimal Routing Algorithm for Triplet-Based WK-recursive Network.
Proceedings of the 20th IEEE International Conference on High Performance Computing and Communications; 16th IEEE International Conference on Smart City; 4th IEEE International Conference on Data Science and Systems, 2018

2017
An evaluation power model for TriBA based application mapping and memory-on-chip.
Proceedings of the 13th International Conference on Natural Computation, 2017

2014
An adaptive and hierarchical task scheduling scheme for multi-core clusters.
Parallel Comput., 2014

Optimal Pipeline Performance via Transactional Slice with No Branch Prediction Overhead.
Proceedings of the UKSim-AMSS 16th International Conference on Computer Modelling and Simulation, 2014


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