Xiaoji Ye

According to our database1, Xiaoji Ye authored at least 17 papers between 2006 and 2011.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2011
Hierarchical Multialgorithm Parallel Circuit Simulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

2010
Exact Time-Domain Second-Order Adjoint-Sensitivity Computation for Linear Circuit Analysis and Optimization.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

Scalable Analysis of Mesh-Based Clock Distribution Networks Using Application-Specific Reduced Order Modeling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Accurate clock mesh sizing via sequential quadraticprogramming.
Proceedings of the 2010 International Symposium on Physical Design, 2010

On-the-fly runtime adaptation for efficient execution of parallel multi-algorithm circuit simulation.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Tradeoff analysis and optimization of power delivery networks with on-chip voltage regulation.
Proceedings of the 47th Design Automation Conference, 2010

Parallel program performance modeling for runtime optimization of multi-algorithm circuit simulation.
Proceedings of the 47th Design Automation Conference, 2010

2009
An application-specific adjoint sensitivity analysis framework for clock mesh sensitivity computation.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Leveraging efficient parallel pattern search for clock mesh optimization.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

2008
Accelerating Clock Mesh Simulation Using Matrix-Level Macromodels and Dynamic Time Step Rounding.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

MAPS: multi-algorithm parallel circuit simulation.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

WavePipe: parallel transient simulation of analog and digital circuits on multi-core shared-memory machines.
Proceedings of the 45th Design Automation Conference, 2008

2007
Fast Variational Interconnect Delay and Slew Computation Using Quadratic Models.
IEEE Trans. Very Large Scale Integr. Syst., 2007

Analysis of large clock meshes via harmonic-weighted model order reduction and port sliding.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Statistical Leakage Power Minimization Using Fast Equi-Slack Shell Based Optimization.
Proceedings of the 44th Design Automation Conference, 2007

Efficient Frequency-Domain Simulation of Massive Clock Meshes Using Parallel Harmonic Balance.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006
Practical variation-aware interconnect delay and slew analysis for statistical timing verification.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006


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